| /Linux-v6.1/drivers/bus/ |
| D | bt1-axi.c | 8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
37 * @qos_regs: AXI Interconnect QoS tuning registers.
40 * @aclk: AXI reference clock.
41 * @arst: AXI Interconnect reset line.
60 struct bt1_axi *axi = data; in bt1_axi_isr() local
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
66 dev_crit_ratelimited(axi->dev, in bt1_axi_isr()
67 "AXI-bus fault %d: %s at 0x%x%08x\n", in bt1_axi_isr()
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| /Linux-v6.1/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 230 - const: axi # AXI reset
255 - const: master_bus # Master AXI clock
256 - const: slave_bus # Slave AXI clock
278 - const: master_bus # Master AXI clock
279 - const: slave_bus # Slave AXI clock
285 - const: axi_m # AXI master reset
286 - const: axi_s # AXI slave reset
292 - const: axi_m_sticky # AXI sticky reset
312 - const: bus_master # Master AXI clock
313 - const: bus_slave # Slave AXI clock
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| D | xilinx-pcie.txt | 1 * Xilinx AXI PCIe Root Port Bridge DT description
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
11 - interrupts: Should contain AXI PCIe interrupt
42 pci_express: axi-pcie@50000000 {
46 compatible = "xlnx,axi-pcie-host-1.00.a";
66 pci_express: axi-pcie@10000000 {
70 compatible = "xlnx,axi-pcie-host-1.00.a";
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| /Linux-v6.1/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
22 - xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
23 - xlnx,axi-str-rxd-tdata-width: Should be <0x20>
24 - xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL"
25 - xlnx,axi-str-txc-tdata-width: Should be <0x20>
26 - xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
27 - xlnx,axi-str-txd-tdata-width: Should be <0x20>
28 - xlnx,axis-tdest-width: AXI-Stream TDEST width (ignored by the driver)
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| D | Kconfig | 3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
12 to the AXI Ethernet without the need to use DMA.
|
| /Linux-v6.1/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
47 Optional properties for AXI DMA and MCDMA:
61 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
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| /Linux-v6.1/Documentation/devicetree/bindings/dma/ |
| D | snps,dw-axi-dmac.yaml | 4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
14 Synopsys DesignWare AXI DMA Controller DT Binding
22 - snps,axi-dma-1.01a
23 - intel,kmb-axi-dma
66 Number of AXI masters supported by the hardware.
72 AXI data width supported by hardware.
91 snps,axi-max-burst-len:
93 Restrict master AXI burst length by value specified in this property.
94 If this property is missing the maximum AXI burst length supported by
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| D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
7 - clocks: Phandle and specifier to the controllers AXI interface clock
26 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
27 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
43 compatible = "adi,axi-dmac-1.00.a";
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-axi-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
7 title: Allwinner A10 AXI Clock
21 - allwinner,sun4i-a10-axi-clk
22 - allwinner,sun8i-a23-axi-clk
44 axi@1c20054 {
46 compatible = "allwinner,sun4i-a10-axi-clk";
49 clock-output-names = "axi";
55 compatible = "allwinner,sun8i-a23-axi-clk";
58 clock-output-names = "axi";
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| D | baikal,bt1-ccu-div.yaml | 26 3) AXI-bus clock dividers (AXI) - described in this binding file.
38 +----+ | | | +-|AXI|-|- AXI-bus
52 domain (like AXI-bus or System Device consumers). The dividers have the
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
79 are called AXI-bus CCU. Both of them use the common clock bindings with no
82 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
90 const: baikal,bt1-ccu-axi
125 - baikal,bt1-ccu-axi
150 # AXI-bus Clock Control Unit node:
155 compatible = "baikal,bt1-ccu-axi";
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| D | adi,axi-clkgen.yaml | 4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Binding for Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
50 compatible = "adi,axi-clkgen-2.00.a";
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| /Linux-v6.1/Documentation/devicetree/bindings/fpga/ |
| D | xilinx-pr-decoupler.txt | 10 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
13 The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
17 that can occur if AXI transactions are interrupted by DFX
26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by
27 "xlnx,dfx-axi-shutdown-manager"
46 Dynamic Function eXchange AXI shutdown manager:
48 compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
49 "xlnx,dfx-axi-shutdown-manager";
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| /Linux-v6.1/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 3 * Definitions for Xilinx Axi Ethernet device driver.
72 /* Axi DMA Register definitions */
144 /* Axi Ethernet registers definition */
179 /* Bit Masks for Axi Ethernet RAF register */
198 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
203 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
223 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
227 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
231 /* Bit masks for Axi Ethernet RCW1 register */
247 /* Bit masks for Axi Ethernet TC register */
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| /Linux-v6.1/Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-axi.yaml | 5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
8 title: Baikal-T1 AXI-bus
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
21 an IRQ is raised and a faulty situation is reported to the AXI EHB
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
31 const: baikal,bt1-axi
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
37 - description: AXI EHB MMIO system controller registers
87 compatible = "baikal,bt1-axi", "simple-bus";
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| D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
9 The cores on the AXI bus are automatically detected by bcma with the
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
|
| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
10 Management configuration is done through the AXI interface, while payload is
11 sent and received through means of an AXI DMA controller. This driver
12 includes the DMA driver code, so this driver is incompatible with AXI DMA
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
21 and length of the AXI DMA controller IO space, unless
47 s_axi_lite_clk: Clock for AXI register slave interface
64 for the AXI DMA controller used by this device.
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | adi,axi-spdif-tx.txt | 1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
7 The controller expects two clocks, the clock used for the AXI interface and
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
24 compatible = "adi,axi-spdif-tx-1.00.a";
27 clock-names = "axi", "ref";
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| D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
28 compatible = "adi,axi-i2s-1.00.a";
31 clock-names = "axi", "ref";
|
| /Linux-v6.1/sound/soc/adi/ |
| D | Makefile | 2 snd-soc-adi-axi-i2s-objs := axi-i2s.o
3 snd-soc-adi-axi-spdif-objs := axi-spdif.o
5 obj-$(CONFIG_SND_SOC_ADI_AXI_I2S) += snd-soc-adi-axi-i2s.o
6 obj-$(CONFIG_SND_SOC_ADI_AXI_SPDIF) += snd-soc-adi-axi-spdif.o
|
| /Linux-v6.1/Documentation/devicetree/bindings/hwmon/ |
| D | adi,axi-fan-control.yaml | 5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
8 title: Analog Devices AXI FAN Control
14 Bindings for the Analog Devices AXI FAN Control driver. Spefications of the
22 - adi,axi-fan-control-1.00.a
51 fpga_axi: fpga-axi {
55 axi_fan_control: axi-fan-control@80000000 {
56 compatible = "adi,axi-fan-control-1.00.a";
|
| /Linux-v6.1/Documentation/devicetree/bindings/iio/adc/ |
| D | adi,axi-adc.yaml | 4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
7 title: Analog Devices AXI ADC IP core
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
26 - adi,axi-adc-10.0.a
53 axi-adc@44a00000 {
54 compatible = "adi,axi-adc-10.0.a";
|
| D | xilinx-xadc.txt | 10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
33 when using the axi-xadc or the axi-system-management-wizard this must be
34 the clock that provides the clock to the AXI bus interface of the core.
110 compatible = "xlnx,axi-xadc-1.00.a";
|
| /Linux-v6.1/arch/arc/plat-axs10x/ |
| D | axs10x.c | 122 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
125 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
128 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
132 * MB AXI Tunnel Master, which also has a mem map setup
134 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
135 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
149 /* MB AXI Target slaves */
156 /* MB AXI masters */
183 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
[all …]
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| /Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-dwc-qos-eth.c | 48 if (!plat_dat->axi) { in dwc_eth_dwmac_config_dt()
49 plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL); in dwc_eth_dwmac_config_dt()
51 if (!plat_dat->axi) in dwc_eth_dwmac_config_dt()
55 plat_dat->axi->axi_lpi_en = device_property_read_bool(dev, in dwc_eth_dwmac_config_dt()
58 &plat_dat->axi->axi_wr_osr_lmt)) { in dwc_eth_dwmac_config_dt()
63 plat_dat->axi->axi_wr_osr_lmt = 1; in dwc_eth_dwmac_config_dt()
69 plat_dat->axi->axi_wr_osr_lmt--; in dwc_eth_dwmac_config_dt()
73 &plat_dat->axi->axi_rd_osr_lmt)) { in dwc_eth_dwmac_config_dt()
78 plat_dat->axi->axi_rd_osr_lmt = 1; in dwc_eth_dwmac_config_dt()
84 plat_dat->axi->axi_rd_osr_lmt--; in dwc_eth_dwmac_config_dt()
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| D | stmmac_pci.c | 63 /* TODO: AXI */ in stmmac_default_data()
120 /* Axi Configuration */ in snps_gmac5_default_data()
121 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL); in snps_gmac5_default_data()
122 if (!plat->axi) in snps_gmac5_default_data()
125 plat->axi->axi_wr_osr_lmt = 31; in snps_gmac5_default_data()
126 plat->axi->axi_rd_osr_lmt = 31; in snps_gmac5_default_data()
128 plat->axi->axi_fb = false; in snps_gmac5_default_data()
129 plat->axi->axi_blen[0] = 4; in snps_gmac5_default_data()
130 plat->axi->axi_blen[1] = 8; in snps_gmac5_default_data()
131 plat->axi->axi_blen[2] = 16; in snps_gmac5_default_data()
[all …]
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