Lines Matching full:axi
122 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
125 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
128 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
132 * MB AXI Tunnel Master, which also has a mem map setup
134 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
135 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
149 /* MB AXI Target slaves */
156 /* MB AXI masters */
183 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
184 * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
206 * memmap for MB AXI Masters
207 * Same mem map for all perip controllers as well as MB AXI Tunnel Master
261 /* AXI tunnel memory map (incoming traffic from MB into CPU Card */ in axs101_early_init()