Searched full:atf (Results 1 – 20 of 20) sorted by relevance
116 /* scratchx(0) CSR used for ATF->non-secure SW communication.182 /* scratchx(1) CSR used for non-secure SW->ATF communication
97 /* UART should keep working in ATF after suspend and before resume */109 /* SRAMB is used as ATF runtime memory, and should be always on */
22 The ATF smc function id used by the firmware.
53 /* DDR3 ATF default */
35 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
69 * the value from ATF instead. in imx8mq_soc_revision()
86 /* Shared with ATF on this platform */
16 atf-sram@0 {
17 atf-sram@0 {
19 atf-sram@0 {
12 ATF | |
87 /* Some bits of BCMA_IOCTL set by HW/ATF and should not change */ in platform_bgmac_clk_enable()
23 /* UUID used to probe ATF service. */
33 execution environments. e.g. ATF.
705 /* Follow the same order than what the Cortex-M3 does (ATF code) */ in armada_3700_periph_clock_resume()
129 * (no direct communication with ATF).
641 * As per comment in ATF source code:
2956 /* ATF configuration.2957 * 1 - Enable ATF2958 * 0 - Disable ATF
1114 type = "83977ATF"; in decode_winbond()1133 type = "83877ATF"; in decode_winbond()
2362 * (e.g., ATF). Thus, the bus should be initialized and ready and in mlxbf_i2c_probe()
