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/Linux-v5.15/include/linux/
Dmath64.h10 #if BITS_PER_LONG == 64
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
[all …]
Dexportfs.h33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
58 * 32 bit generation number,
[all …]
/Linux-v5.15/drivers/mtd/nand/raw/
Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
[all …]
/Linux-v5.15/lib/math/
Ddiv64.c10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
27 /* Not needed on 64bit architectures */
38 /* Reduce the thing a bit first */ in __div64_32()
67 * div_s64_rem - signed 64bit divide with 64bit divisor and remainder
68 * @dividend: 64bit dividend
69 * @divisor: 64bit divisor
70 * @remainder: 64bit remainder
93 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
94 * @dividend: 64bit dividend
[all …]
/Linux-v5.15/lib/
Datomic64_test.c20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
40 test(bit, op##_release, ##args); \
[all …]
/Linux-v5.15/arch/riscv/
DKconfig7 config 64BIT config
10 config 32BIT
42 select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
50 select GENERIC_ATOMIC64 if !64BIT
64 select GENERIC_TIME_VSYSCALL if MMU && 64BIT
69 select HAVE_ARCH_KASAN if MMU && 64BIT
70 select HAVE_ARCH_KASAN_VMALLOC if MMU && 64BIT
71 select HAVE_ARCH_KFENCE if MMU && 64BIT
77 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
79 select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
[all …]
/Linux-v5.15/drivers/net/ethernet/cavium/liquidio/
Dcn23xx_pf_regs.h74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
145 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
147 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
[all …]
Dcn23xx_vf_regs.h52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
87 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
92 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
93 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
94 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
95 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
[all …]
Dcn66xx_regs.h89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
121 /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */
127 /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data &
132 /* 1 register (64-bit) - Number of instructions to read at one time
137 /* 1 register (64-bit) - Assign Input ring to MAC port
162 #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22)
[all …]
/Linux-v5.15/arch/x86/um/
DKconfig13 config 64BIT config
14 bool "64-bit kernel" if "$(SUBARCH)" = "x86"
18 def_bool !64BIT
27 def_bool 64BIT
31 bool "Three-level pagetables" if !64BIT
32 default 64BIT
38 However, this it experimental on 32-bit architectures, so if unsure say
39 N (on x86-64 it's automatically enabled, instead, as it's safe there).
42 def_bool !64BIT
45 def_bool !64BIT
/Linux-v5.15/drivers/gpio/
Dgpio-xilinx.c31 #define XGPIO_GIER_IE BIT(31)
64 DECLARE_BITMAP(hw_map, 64);
65 DECLARE_BITMAP(sw_map, 64);
66 DECLARE_BITMAP(state, 64);
67 DECLARE_BITMAP(last_irq_read, 64);
68 DECLARE_BITMAP(dir, 64);
72 DECLARE_BITMAP(enable, 64);
73 DECLARE_BITMAP(rising_edge, 64);
74 DECLARE_BITMAP(falling_edge, 64);
78 static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) in xgpio_from_bit() argument
[all …]
/Linux-v5.15/drivers/net/ethernet/broadcom/
Dtg3.h21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
285 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
286 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
307 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
308 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
309 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
310 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
311 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
[all …]
/Linux-v5.15/arch/parisc/
DKconfig4 select ARCH_32BIT_OFF_T if !64BIT
30 select GENERIC_ATOMIC64 if !64BIT
86 default "arch/parisc/configs/generic-32bit_defconfig" if !64BIT
87 default "arch/parisc/configs/generic-64bit_defconfig" if 64BIT
137 default 3 if 64BIT && PARISC_PAGE_SIZE_4KB
151 that can run on all 32-bit PA CPUs (albeit not optimally fast),
154 Specifying "PA8000" here will allow you to select a 64-bit kernel
161 712, 715/64, 715/80, 715/100, 715/100XC, 725/100, 743, 748,
221 config 64BIT config
222 bool "64-bit kernel"
[all …]
/Linux-v5.15/drivers/acpi/acpica/
Dtbfadt.c166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
188 * The 64-bit Address field is non-aligned in the byte packed in acpi_tb_init_generic_address()
206 * address32 - 32-bit address of the register
207 * address64 - 64-bit address of the register
209 * RETURN: The resolved 64-bit address
211 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
217 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
222 * By default, as per the ACPICA specification, a valid 64-bit address is
223 * used regardless of the value of the 32-bit address. However, this
[all …]
/Linux-v5.15/arch/s390/include/asm/
Delf.h13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
25 #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */
26 #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
[all …]
/Linux-v5.15/arch/s390/crypto/
Dcrc32be-vx.S9 * bit first (BE).
37 * R1 = x4*128+64 mod P(x)
39 * R3 = x128+64 mod P(x)
44 * Barret reduction constant, u, is defined as floor(x**64 / P(x)).
82 * %r4: Length of the buffer, must be 64 bytes or greater.
102 /* Load a 64-byte data chunk and XOR with CRC */
103 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
105 aghi %r3,64 /* BUF = BUF + 64 */
106 aghi %r4,-64 /* LEN = LEN - 64 */
109 cghi %r4,64
[all …]
/Linux-v5.15/include/xen/interface/
Dcallback.h45 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
59 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
60 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
61 * ('32-on-32-on-64', '32-on-64-on-64')
62 * [nb. also 64-bit guest applications on Intel CPUs
63 * ('64-on-64-on-64'), but syscall is preferred]
68 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
69 * ('32-on-32-on-64', '32-on-64-on-64')
/Linux-v5.15/arch/x86/kvm/vmx/
Dvmx_ops.h25 "16-bit accessor invalid for 64-bit field"); in vmcs_check16()
27 "16-bit accessor invalid for 64-bit high field"); in vmcs_check16()
29 "16-bit accessor invalid for 32-bit high field"); in vmcs_check16()
31 "16-bit accessor invalid for natural width field"); in vmcs_check16()
37 "32-bit accessor invalid for 16-bit field"); in vmcs_check32()
39 "32-bit accessor invalid for 64-bit field"); in vmcs_check32()
41 "32-bit accessor invalid for 64-bit high field"); in vmcs_check32()
43 "32-bit accessor invalid for natural width field"); in vmcs_check32()
49 "64-bit accessor invalid for 16-bit field"); in vmcs_check64()
51 "64-bit accessor invalid for 64-bit high field"); in vmcs_check64()
[all …]
/Linux-v5.15/drivers/infiniband/hw/bnxt_re/
Dqplib_sp.h125 #define BNXT_QPLIB_ACCESS_LOCAL_WRITE BIT(0)
126 #define BNXT_QPLIB_ACCESS_REMOTE_READ BIT(1)
127 #define BNXT_QPLIB_ACCESS_REMOTE_WRITE BIT(2)
128 #define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC BIT(3)
129 #define BNXT_QPLIB_ACCESS_MW_BIND BIT(4)
130 #define BNXT_QPLIB_ACCESS_ZERO_BASED BIT(5)
131 #define BNXT_QPLIB_ACCESS_ON_DEMAND BIT(6)
136 /* seq_err_naks_rcvd is 64 b */
138 /* max_retry_exceeded is 64 b */
140 /* rnr_naks_rcvd is 64 b */
[all …]
/Linux-v5.15/arch/mips/include/asm/
Dmips-cm.h39 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
40 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
45 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
130 GCR_ACCESSOR_RO(64, 0x000, config)
138 GCR_ACCESSOR_RW(64, 0x008, base)
166 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
167 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
170 GCR_ACCESSOR_RW(64, 0x040, error_mask)
173 GCR_ACCESSOR_RW(64, 0x048, error_cause)
179 GCR_ACCESSOR_RW(64, 0x050, error_addr)
[all …]
/Linux-v5.15/Documentation/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
30 run 32-bit code on one of these transitionary platforms then you would
38 allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
[all …]
/Linux-v5.15/arch/mips/include/asm/octeon/
Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
[all …]
/Linux-v5.15/arch/mips/
DKconfig5 select ARCH_32BIT_OFF_T if !64BIT
7 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
20 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
32 select GENERIC_ATOMIC64 if !64BIT
60 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
68 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
96 select MODULES_USE_ELF_RELA if MODULES && 64BIT
368 select CPU_DADDI_WORKAROUNDS if 64BIT
[all …]
/Linux-v5.15/arch/mips/kernel/
Dunaligned.c295 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
296 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
297 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
298 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
299 * instructions on 32-bit kernels. in emulate_load_store_insn()
312 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
318 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
319 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
320 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
321 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
[all …]
/Linux-v5.15/drivers/net/ethernet/cavium/
DKconfig18 depends on 64BIT && PCI
31 depends on 64BIT && PCI
37 depends on 64BIT && PCI
47 depends on 64BIT && PCI
56 depends on 64BIT && PCI
67 depends on 64BIT && PCI
93 depends on 64BIT && PCI_MSI

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