295 		 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_insn()
296 		 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_insn()
297 		 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_insn()
298 		 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_insn()
299 		 * instructions on 32-bit kernels.  in emulate_load_store_insn()
312 		/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_insn()
318 		 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_insn()
319 		 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_insn()
320 		 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_insn()
321 		 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_insn()
322 		 * instructions on 32-bit kernels.  in emulate_load_store_insn()
335 		/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_insn()
373 		 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_insn()
374 		 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_insn()
375 		 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_insn()
376 		 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_insn()
377 		 * instructions on 32-bit kernels.  in emulate_load_store_insn()
390 		/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_insn()
567 /* Recode table from 16-bit register notation to 32-bit GPR. */
570 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1078 	 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_microMIPS()
1079 	 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_microMIPS()
1080 	 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_microMIPS()
1081 	 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_microMIPS()
1082 	 * instructions on 32-bit kernels.  in emulate_load_store_microMIPS()
1094 	/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_microMIPS()
1100 	 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_microMIPS()
1101 	 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_microMIPS()
1102 	 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_microMIPS()
1103 	 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_microMIPS()
1104 	 * instructions on 32-bit kernels.  in emulate_load_store_microMIPS()
1116 	/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_microMIPS()
1142 	 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_microMIPS()
1143 	 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_microMIPS()
1144 	 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_microMIPS()
1145 	 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_microMIPS()
1146 	 * instructions on 32-bit kernels.  in emulate_load_store_microMIPS()
1158 	/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_microMIPS()
1344 		 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_MIPS16e()
1345 		 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_MIPS16e()
1346 		 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_MIPS16e()
1347 		 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_MIPS16e()
1348 		 * instructions on 32-bit kernels.  in emulate_load_store_MIPS16e()
1361 		/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_MIPS16e()
1368 		 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_MIPS16e()
1369 		 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_MIPS16e()
1370 		 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_MIPS16e()
1371 		 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_MIPS16e()
1372 		 * instructions on 32-bit kernels.  in emulate_load_store_MIPS16e()
1385 		/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_MIPS16e()
1416 		 * A 32-bit kernel might be running on a 64-bit processor.  But  in emulate_load_store_MIPS16e()
1417 		 * if we're on a 32-bit processor and an i-cache incoherency  in emulate_load_store_MIPS16e()
1418 		 * or race makes us see a 64-bit instruction here the sdl/sdr  in emulate_load_store_MIPS16e()
1419 		 * would blow up, so for now we don't handle unaligned 64-bit  in emulate_load_store_MIPS16e()
1420 		 * instructions on 32-bit kernels.  in emulate_load_store_MIPS16e()
1433 		/* Cannot handle 64-bit instructions in 32-bit kernel */  in emulate_load_store_MIPS16e()
1505 		 * 16-bit mode?  in do_ade()