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/Linux-v6.6/drivers/staging/vt6655/
Drf.c55 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
56 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
57 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
58 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
59 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
60 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
61 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
62 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
63 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
64 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
[all …]
/Linux-v6.6/arch/powerpc/boot/dts/
Dac14xx.dts26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
174 at24@30 {
262 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
263 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
/Linux-v6.6/drivers/clk/
Dclk-tps68470.c41 * frequency range of 3 MHz to 27 MHz by a programmable
44 * of 4 MHz to 64 MHz in increments of 0.1 MHz.
46 * hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
49 * PLL_REF_CLK = input clk / XTALDIV[7:0] + 30)
53 * BOOST should be as close as possible to 2Mhz
56 * BUCK should be as close as possible to 5.2Mhz
60 * 20Mhz 170 32 1 19.2Mhz
61 * 20Mhz 170 40 1 20Mhz
62 * 20Mhz 170 80 1 24Mhz
Dclk-gemini.c29 #define PLL_OSC_SEL BIT(30)
134 /* We support 33 and 66 MHz */ in gemini_pci_round_rate()
228 /* Manual says to always set BIT 30 (CPU1) to 1 */ in gemini_reset()
353 * This clock is supposed to be 27MHz as this is an exact multiple in gemini_clk_probe()
432 * XTAL is the crystal oscillator, 60 or 30 MHz selected from in gemini_cc_init()
440 pr_debug("main crystal @%lu MHz\n", freq / 1000000); in gemini_cc_init()
445 /* If we run on 30 MHz crystal we have to multiply with two */ in gemini_cc_init()
/Linux-v6.6/include/linux/mfd/
Dsi476x-platform.h72 SI476X_ICIN_IC_LINK = 30,
80 SI476X_ICIP_IC_LINK = 30,
87 SI476X_ICON_IC_LINK = 30,
94 SI476X_ICOP_IC_LINK = 30,
202 * SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
203 * SI476X_XTAL_36P4_MHZ - 36.4 Mhz
204 * SI476X_XTAL_37P8_MHZ - 37.8 Mhz
/Linux-v6.6/drivers/media/dvb-frontends/
Ds5h1432.c90 /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */ in s5h1432_set_channel_bandwidth()
199 msleep(30); in s5h1432_set_frontend()
201 msleep(30); in s5h1432_set_frontend()
223 msleep(30); in s5h1432_set_frontend()
225 msleep(30); in s5h1432_set_frontend()
269 /*Set 3.3MHz as default IF frequency */ in s5h1432_init()
285 msleep(30); in s5h1432_init()
364 .frequency_min_hz = 177 * MHz,
365 .frequency_max_hz = 858 * MHz,
/Linux-v6.6/drivers/watchdog/
Dsc520_wdt.c84 * char to /dev/watchdog every 30 seconds.
87 #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
108 #define WDT_EXP_SEL_01 0x0001 /* [01] Time-out = 496 us (with 33 Mhz clk). */
109 #define WDT_EXP_SEL_02 0x0002 /* [02] Time-out = 508 ms (with 33 Mhz clk). */
110 #define WDT_EXP_SEL_03 0x0004 /* [03] Time-out = 1.02 s (with 33 Mhz clk). */
111 #define WDT_EXP_SEL_04 0x0008 /* [04] Time-out = 2.03 s (with 33 Mhz clk). */
112 #define WDT_EXP_SEL_05 0x0010 /* [05] Time-out = 4.07 s (with 33 Mhz clk). */
113 #define WDT_EXP_SEL_06 0x0020 /* [06] Time-out = 8.13 s (with 33 Mhz clk). */
114 #define WDT_EXP_SEL_07 0x0040 /* [07] Time-out = 16.27s (with 33 Mhz clk). */
115 #define WDT_EXP_SEL_08 0x0080 /* [08] Time-out = 32.54s (with 33 Mhz clk). */
Daspeed_wdt.c101 * and bit 30 represents push-pull or open-drain. With respect to write, magic
111 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
117 /* 32 bits at 1MHz, in milliseconds */
119 #define WDT_DEFAULT_TIMEOUT 30
358 * - ast2400 wdt can run at PCLK, or 1MHz in aspeed_wdt_probe()
359 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1 in aspeed_wdt_probe()
360 * - ast2600 always runs at 1MHz in aspeed_wdt_probe()
362 * Set the ast2400 to run at 1MHz as it simplifies the driver. in aspeed_wdt_probe()
397 * Primarily, ensure we're using the 1MHz clock source. in aspeed_wdt_probe()
436 * The watchdog is always configured with a 1MHz source, so in aspeed_wdt_probe()
/Linux-v6.6/drivers/net/wireless/ath/ath10k/
Drx_desc.h43 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30),
370 #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30)
585 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30)
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
782 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
786 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
790 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
[all …]
/Linux-v6.6/drivers/clk/ingenic/
Djz4760-cgu.c20 #define MHZ (1000 * 1000) macro
63 /* The frequency after the N divider must be between 1 and 50 MHz. */ in jz4760_cgu_calc_m_n_od()
64 n = parent_rate / (1 * MHZ); in jz4760_cgu_calc_m_n_od()
69 rate /= MHZ; in jz4760_cgu_calc_m_n_od()
70 parent_rate /= MHZ; in jz4760_cgu_calc_m_n_od()
243 .mux = { CGU_REG_LPCDR, 30, 1 },
260 .mux = { CGU_REG_PCMCDR, 30, 2 },
268 .mux = { CGU_REG_I2SCDR, 30, 2 },
275 .mux = { CGU_REG_USBCDR, 30, 2 },
382 .gate = { CGU_REG_LCR, 30, false, 150 },
/Linux-v6.6/Documentation/devicetree/bindings/usb/
Drockchip,dwc3.yaml54 Controller reference clock, must to be 24 MHz
56 Controller suspend clock, must to be 24 MHz or 32 KHz
58 Master/Core clock, must to be >= 62.5 MHz for SS
59 operation and >= 30MHz for HS operation
Drockchip,rk3399-dwc3.yaml27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
/Linux-v6.6/drivers/clk/mvebu/
Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
172 { "crypto1_enc", NULL, 30 },
/Linux-v6.6/drivers/mmc/host/
Dsdhci-of-arasan.c203 * met at 25MHz for Default Speed mode, those controllers work at
204 * 19MHz instead
401 * requirements met at 25MHz for Default Speed mode, in sdhci_arasan_set_clock()
402 * those controllers work at 19MHz instead. in sdhci_arasan_set_clock()
751 /* For 50MHz clock, 30 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
752 tap_max = 30; in sdhci_zynqmp_sdcardclk_set_phase()
755 /* For 100MHz clock, 15 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
760 /* For 200MHz clock, 8 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
820 /* For 50MHz clock, 120 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
824 /* For 100MHz clock, 60 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
[all …]
/Linux-v6.6/drivers/net/wireless/intel/iwlwifi/cfg/
D9000.c16 #define IWL9000_UCODE_API_MIN 30
163 const char iwl9162_160_name[] = "Intel(R) Wireless-AC 9162 160MHz";
164 const char iwl9260_160_name[] = "Intel(R) Wireless-AC 9260 160MHz";
165 const char iwl9270_160_name[] = "Intel(R) Wireless-AC 9270 160MHz";
166 const char iwl9461_160_name[] = "Intel(R) Wireless-AC 9461 160MHz";
167 const char iwl9462_160_name[] = "Intel(R) Wireless-AC 9462 160MHz";
168 const char iwl9560_160_name[] = "Intel(R) Wireless-AC 9560 160MHz";
171 "Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz";
175 "Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz";
179 "Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz";
/Linux-v6.6/drivers/video/fbdev/
Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
/Linux-v6.6/drivers/clk/ti/
Dclk-33xx.c19 "clk-24mhz-clkctrl:0000:0",
152 "l3-aon-clkctrl:0000:30",
187 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
207 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
241 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
243 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
/Linux-v6.6/arch/arm/mach-rockchip/
Dpm.c143 * source. Therefore set 30ms on a 32kHz clock for pmic in rk3288_slp_mode_set()
144 * stabilization. Similar 30ms on 24MHz for the other in rk3288_slp_mode_set()
147 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); in rk3288_slp_mode_set()
151 osc_disable ? 32 * 30 : 0); in rk3288_slp_mode_set()
163 /* 30ms on a 24MHz clock for pmic stabilization */ in rk3288_slp_mode_set()
164 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); in rk3288_slp_mode_set()
/Linux-v6.6/drivers/ata/
Dpata_hpt37x.c3 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
26 #define DRV_VERSION "0.6.30"
56 * 30 PIO_MST enable. If set, the chip is in bus master mode during
595 * @freq: Reported frequency in MHz
598 * and 3 for 66Mhz)
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/clock/st/
Dst,quadfs.txt5 or 660MHz (from a 30MHz oscillator input) as the input to the digital
/Linux-v6.6/drivers/phy/ti/
Dphy-ti-pipe3.c74 #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
75 #define MEM_DLL_TRIM_SHIFT 30
78 #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
79 #define MEM_DLL_PHINT_RATE_SHIFT 30
186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
[all …]
/Linux-v6.6/drivers/media/i2c/
Dov5695.c26 /* 45Mhz * 4 Binning */
118 * Xclk 24Mhz
119 * Pclk 45Mhz
124 * max_framerate 30fps
293 * Xclk 24Mhz
294 * Pclk 45Mhz
299 * max_framerate 30fps
335 * Xclk 24Mhz
336 * Pclk 45Mhz
341 * max_framerate 30fps
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu9_driver_if.h121 uint16_t Freq; /* in MHz */
320 /* ACG Frequency Table, in Mhz */
330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
331 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
377 uint16_t avgPsmCount[30];
378 uint16_t minPsmCount[30];
379 float avgPsmVoltage[30];
380 float minPsmVoltage[30];
/Linux-v6.6/tools/power/cpupower/utils/helpers/
Dmisc.c93 char linebuf[30] = {}; in cpupower_set_epp()
103 if (cpupower_write_sysfs(path, linebuf, 30) <= 0) in cpupower_set_epp()
237 printf("%u.%03u MHz", ((unsigned int)speed / 1000), in print_speed()
252 printf("%u MHz", ((unsigned int)speed / 1000)); in print_speed()
257 printf("%u.%01u MHz", ((unsigned int)speed / 1000), in print_speed()

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