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/Linux-v5.10/arch/m68k/include/uapi/asm/
Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/Linux-v5.10/arch/arm/mach-omap2/
Dopp2xxx.h71 #define R1_CLKSEL_USB (4 << 25)
88 #define R2_CLKSEL_USB (2 << 25)
105 #define RB_CLKSEL_USB (1 << 25)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
[all …]
Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
85 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
97 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
120 den = 25; in realtime_counter_init()
136 /* Program it for 38.4 MHz */ in realtime_counter_init()
138 den = 25; in realtime_counter_init()
/Linux-v5.10/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
66 xtal25mhz: xtal25mhz@25M {
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
146 /* TIMER0 runs directly on the 25MHz chrystal */
152 /* TIMER1 runs @ 1MHz */
158 /* TIMER2 runs @ 1MHz */
[all …]
Ddove-cubox.dts52 /* 25MHz reference crystal */
97 /* connect xtal input to 25MHz reference */
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmicrel.txt22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dintel_gt_clock_utils.c10 #define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
11 #define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
12 #define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
91 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS in intel_gt_ns_to_pm_interval()
99 val = roundup(val, 25); in intel_gt_ns_to_pm_interval()
/Linux-v5.10/drivers/clk/uniphier/
Dclk-uniphier-sys.c83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
101 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
102 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/Linux-v5.10/drivers/clk/spear/
Dspear1340_clock.c110 #define SPEAR1340_DMA_CLK_ENB 25
167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
[all …]
Dspear1310_clock.c112 #define SPEAR1310_DMA_CLK_ENB 25
203 #define SPEAR1310_CAN1_CLK_ENB 25
234 /* PCLK 24MHz */
235 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
236 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
237 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
239 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
240 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
246 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
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/Linux-v5.10/drivers/media/tuners/
Dqt1010.c77 { QT1010_RD, 0x23, 0xff }, /* 25 c read */ in qt1010_set_params()
102 #define FREQ1 32000000 /* 32 MHz */ in qt1010_set_params()
103 #define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ in qt1010_set_params()
117 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */ in qt1010_set_params()
118 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */ in qt1010_set_params()
119 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */ in qt1010_set_params()
125 /* 07 - set frequency: 32 MHz scale */ in qt1010_set_params()
128 /* 09 - changes every 8/24 MHz */ in qt1010_set_params()
132 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */ in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
[all …]
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/Linux-v5.10/drivers/clk/mvebu/
Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
169 { "tdm", NULL, 25 },
Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
115 return 25 * 1000 * 1000; in armada_39x_refclk_ratio()
/Linux-v5.10/drivers/ide/
Dopti621.c76 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */ in opti621_set_pio_mode()
77 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */ in opti621_set_pio_mode()
80 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */ in opti621_set_pio_mode()
81 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */ in opti621_set_pio_mode()
108 printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33); in opti621_set_pio_mode()
/Linux-v5.10/drivers/clk/versatile/
Dclk-icst.c107 * 33 or 25 MHz respectively. in vco_get()
262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
267 /* Slam to closest 0.25 MHz */ in icst_round_rate()
273 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
274 * select 25 MHz in icst_round_rate()
438 /* Minimum 12 MHz, VDW = 4 */
441 * Maximum 160 MHz, VDW = 152 for all core modules, but
443 * go to 200 MHz (max VDW = 192).
456 /* Minimum 3 MHz, VDW = 4 */
458 /* Maximum 50 MHz, VDW = 192 */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dsilabs,si5351.txt61 /* 25MHz reference crystal */
78 /* connect xtal input to 25MHz reference */
91 * - set initial clock frequency of 74.25MHz
/Linux-v5.10/Documentation/devicetree/bindings/net/dsa/
Dksz.txt24 125MHz instead of 25MHz.
42 cs-gpios = <&pioC 25 0>;
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
/Linux-v5.10/arch/arm/mach-davinci/
Dsleep.S19 /* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
20 #define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
21 #define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
22 #define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
127 /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
/Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sti.c45 *| MII | n/a | 25Mhz |
48 *| GMII | 125Mhz | 25Mhz |
51 *| RGMII | 125Mhz | 25Mhz |
55 *| RMII | n/a | 25Mhz |
/Linux-v5.10/drivers/mmc/host/
Dsdhci-esdhc-mcf.c21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
162 * RM (25.3.9) sd pin clock must never exceed 25Mhz. in esdhc_mcf_readl_be()
163 * So forcing legacy mode at 25Mhz. in esdhc_mcf_readl_be()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
243 * (25.3.9) sd pin clock must never exceed 25Mhz in esdhc_mcf_pltfm_set_clock()
/Linux-v5.10/include/linux/platform_data/x86/
Dclk-pmc-atom.h16 * @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported
/Linux-v5.10/drivers/ssb/
Dmain.c854 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
855 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
856 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
857 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
861 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
867 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
874 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
875 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
890 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
891 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
[all …]

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