Lines Matching +full:25 +full:mhz

854 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */  in ssb_calc_clock_rate()
855 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */  in ssb_calc_clock_rate()
856 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */  in ssb_calc_clock_rate()
857 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
861 	case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */  in ssb_calc_clock_rate()
867 	case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
874 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */  in ssb_calc_clock_rate()
875 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
890 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */  in ssb_calc_clock_rate()
891 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */  in ssb_calc_clock_rate()
892 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */  in ssb_calc_clock_rate()
893 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */  in ssb_calc_clock_rate()
959 		if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */  in ssb_clockspeed()