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/Linux-v5.10/arch/x86/crypto/
Dsha256-avx-asm.S11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 # This code schedules 1 block at a time, with 4 lanes per block
106 a = %eax define
140 # Rotate values of symbols a...h
149 b = a
150 a = TMP_ define
154 ## compute s0 four at a time and s1 two at a time
155 ## compute W[-16] + W[-7] 4 at a time
158 MY_ROR (25-11), y0 # y0 = e >> (25-11)
[all …]
Dsha256-ssse3-asm.S11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
99 a = %eax define
134 # Rotate values of symbols a...h
143 b = a
144 a = TMP_ define
148 ## compute s0 four at a time and s1 two at a time
149 ## compute W[-16] + W[-7] 4 at a time
152 ror $(25-11), y0 # y0 = e >> (25-11)
153 mov a, y1 # y1 = a
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Dsha256-avx2-asm.S11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
48 # This code schedules 2 blocks at a time, with 4 lanes per block
102 a = %eax define
141 # Rotate values of symbols a...h
151 b = a
152 a = TMP_ define
158 mov a, y3 # y3 = a # MAJA
160 rorx $11, e, y1 # y1 = e >> 11 # S1B
163 or c, y3 # y3 = a|c # MAJA
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/Linux-v5.10/arch/mips/include/asm/
Dunaligned-emul.h22 ".section\t__ex_table,\"a\"\n\t" \
43 ".section\t__ex_table,\"a\"\n\t" \
73 "11:\tli\t%1, %3\n\t" \
76 ".section\t__ex_table,\"a\"\n\t" \
77 STR(PTR)"\t1b, 11b\n\t" \
78 STR(PTR)"\t2b, 11b\n\t" \
79 STR(PTR)"\t3b, 11b\n\t" \
80 STR(PTR)"\t4b, 11b\n\t" \
104 ".section\t__ex_table,\"a\"\n\t" \
127 ".section\t__ex_table,\"a\"\n\t" \
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/Linux-v5.10/tools/testing/selftests/tc-testing/tc-tests/filters/
Dtests.json80 …dd dev $DEV2 protocol ip prio 1 ingress flower dst_mac e4:11:22:11:4a:51 src_mac e4:11:22:11:4a:50…
82 …dd dev $DEV2 protocol ip prio 1 ingress flower dst_mac e4:11:22:11:4a:51 src_mac e4:11:22:11:4a:50…
101 …"$TC filter add dev $DEV2 protocol ip pref 1 ingress flower dst_mac e4:11:22:11:4a:51 action drop",
120 …"$TC filter add dev $DEV2 protocol ip pref 1 ingress flower dst_mac e4:11:22:11:4a:51 action drop",
123 "matchPattern": " dst_mac e4:11:22:11:4a:51",
/Linux-v5.10/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
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/Linux-v5.10/Documentation/ABI/testing/
Dsysfs-class-rapidio10 NOTE: An mport ID is not a RapidIO destination ID assigned to a
36 only fabric enumerating mports have a valid destination ID
39 After enumeration or discovery was performed for a given mport device,
48 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
49 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
50 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0007
51 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0002
52 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0003
53 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0005
54 lrwxrwxrwx 1 root root 0 Feb 11 15:11 device -> ../../../0000:01:00.0
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/Linux-v5.10/arch/m68k/include/asm/
Ddelay.h11 * Delay routines, using a pre-computed "loops_per_jiffy" value.
19 * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
20 * than using a NOP (0x4e71) instruction because it executes in one
22 * for bus cycles to finish. Also fp/a6 isn't likely to cause a
49 * The simpler m68k and ColdFire processors do not have a 32*32->64
50 * multiply instruction. So we need to handle them a little differently.
51 * We use a bit of shifting and a single 32*32->32 multiply to get close.
56 __delay(((((u) * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6)
71 * The definition of __const_udelay is specifically made a macro so that
73 * the delay is a const.
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/Linux-v5.10/tools/thermal/tmon/
Dtmon.84 \fBtmon\fP - A monitoring and testing tool for Linux kernel thermal subsystem
32 - with a built-in Proportional Integral Derivative (\fBPID\fP)
33 controller, user can pair a cooling device to a thermal sensor for
46 The \fB-c --control\fP option sets a cooling device type to control temperature
47 of a thermal zone
70 \fBA \fP active cooling trip point type (fan)
72 \fBA \fP hot trip point type
89 \fBTAB\fP shows tuning pop up panel, choose a letter to modify
124 11 65.0 67 67 0 0 0 0 0 0 0 0 0 0 8 8 8 8 6 0
129 16 65.0 66 66 0 0 0 0 0 0 0 0 0 0 11 11 11 11 6 0
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/Linux-v5.10/arch/powerpc/boot/
Dcrtsavres.S25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
28 * You should have received a copy of the GNU General Public License
33 * As a special exception, if you link this library with files
58 stw 14,-72(11) /* save gp registers */
61 stw 15,-68(11)
64 stw 16,-64(11)
67 stw 17,-60(11)
70 stw 18,-56(11)
73 stw 19,-52(11)
76 stw 20,-48(11)
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/Linux-v5.10/lib/crypto/
Dblake2s-generic.c3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
21 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
22 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
23 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
24 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
25 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
26 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
27 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
28 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
29 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
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/Linux-v5.10/crypto/
Dmd4.c63 #define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s)) argument
64 #define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (u32)0x5A827999,s)) argument
65 #define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (u32)0x6ED9EBA1,s)) argument
69 u32 a, b, c, d; in md4_transform() local
71 a = hash[0]; in md4_transform()
76 ROUND1(a, b, c, d, in[0], 3); in md4_transform()
77 ROUND1(d, a, b, c, in[1], 7); in md4_transform()
78 ROUND1(c, d, a, b, in[2], 11); in md4_transform()
79 ROUND1(b, c, d, a, in[3], 19); in md4_transform()
80 ROUND1(a, b, c, d, in[4], 3); in md4_transform()
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/Linux-v5.10/arch/x86/lib/
Dx86-opcode-map.txt16 # mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix
17 # mnemonics that begin with lowercase 'k' accept a VEX prefix
51 0a: OR Gb,Eb
59 11: ADC Ev,Gv
68 1a: SBB Gb,Eb
85 2a: SUB Gb,Eb
102 3a: CMP Gb,Eb
119 4a: DEC eDX (i64) | REX.WX (o64)
136 5a: POP rDX/r10 (d64)
153 6a: PUSH Ib (d64)
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/Linux-v5.10/tools/arch/x86/lib/
Dx86-opcode-map.txt16 # mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix
17 # mnemonics that begin with lowercase 'k' accept a VEX prefix
51 0a: OR Gb,Eb
59 11: ADC Ev,Gv
68 1a: SBB Gb,Eb
85 2a: SUB Gb,Eb
102 3a: CMP Gb,Eb
119 4a: DEC eDX (i64) | REX.WX (o64)
136 5a: POP rDX/r10 (d64)
153 6a: PUSH Ib (d64)
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/Linux-v5.10/drivers/staging/vt6655/
Ddevice.h50 #define RATE_54M 11
77 /* 0:11A 1:11B 2:11G */
82 /* 0:11a, 1:11b, 2:11gb (only CCK in BasicRate), 3:11ga (OFDM in BasicRate) */
194 u8 byBBType; /* 0:11A, 1:11B, 2:11G */
196 * 0:11a,1:11b,2:11gb (only CCK
197 * in BasicRate), 3:11ga (OFDM in
/Linux-v5.10/tools/testing/selftests/drivers/net/mlxsw/
Dsch_red_core.sh3 # This test sends a >1Gbps stream of traffic from H1, to the switch, which
4 # forwards it to a 1Gbps port. This 1Gbps stream is then looped back to the
11 # A RED Qdisc is installed on $swp3. The configuration is such that the minimum
12 # and maximum size are 1 byte apart, so there is a very clear border under which
28 # | | $h1.11 + | | | $h2.11 + |
49 # | | | $swp1.11 + | | | | $swp2.11 + | |
50 # | | | | | .-----------------+ $swp5.11 | |
53 # | | | $swp2.11 + | | | | | | |
54 # | | +-----------------|-+ | | | | $swp3.11 + | |
67 # | + $h3.10 $h3.11 + |
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/Linux-v5.10/tools/testing/selftests/net/forwarding/
Dsch_tbf_core.sh3 # This test sends a stream of traffic from H1 through a switch, to H2. On the
4 # egress port from the switch ($swp2), a shaper is installed. The test verifies
12 # | + $h1.10 $h1.11 + |
25 # | | + $swp1.10 | | $swp1.11 + | |
29 # | | + $swp2.10 | | $swp2.11 + | |
41 # | + $h2.10 $h2.11 + |
68 vlan_create $dev 11 v$dev $(ipaddr $host 11)/28
69 ip link set dev $dev.11 type vlan egress 0:1
76 vlan_destroy $dev 11
100 flower $TCFLAGS vlan_id 11 action pass
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/Linux-v5.10/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl507c.h4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
49 #define NV507C_DMA_METHOD_OFFSET 11:2
54 #define NV507C_DMA_JUMP_OFFSET 11:2
57 #define NV507C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
61 #define NV507C_PUT_PTR 11:2
63 #define NV507C_GET_PTR 11:2
77 #define NV507C_SET_SEMAPHORE_CONTROL_OFFSET 11:2
88 #define NV507C_SET_NOTIFIER_CONTROL_OFFSET 11:2
110 #define NV507C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0… argument
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/Linux-v5.10/tools/testing/selftests/ftrace/test.d/kprobe/
Dkprobe_syntax_errors.tc60 check_error 'p vfs_read +0(@11):u8[10^' # ARRAY_NO_CLOSE
61 check_error 'p vfs_read +0(@11):u8[10]^a' # BAD_ARRAY_SUFFIX
62 check_error 'p vfs_read +0(@11):u8[^10a]' # BAD_ARRAY_NUM
63 check_error 'p vfs_read +0(@11):u8[^256]' # ARRAY_TOO_BIG
66 check_error 'p vfs_read @11:^unknown_type' # BAD_TYPE
68 check_error 'p vfs_read @11:^b10@a/16' # BAD_BITFIELD
70 check_error 'p vfs_read ^arg123456789012345678901234567890=@11' # ARG_NAME_TOO_LOG
71 check_error 'p vfs_read ^=@11' # NO_ARG_NAME
72 check_error 'p vfs_read ^var.1=@11' # BAD_ARG_NAME
73 check_error 'p vfs_read var1=@11 ^var1=@12' # USED_ARG_NAME
/Linux-v5.10/arch/powerpc/lib/
Dcrtsavres.S26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
29 * You should have received a copy of the GNU General Public License
34 * As a special exception, if you link this library with files
57 stw 14,-72(11) /* save gp registers */
60 stw 15,-68(11)
63 stw 16,-64(11)
66 stw 17,-60(11)
69 stw 18,-56(11)
72 stw 19,-52(11)
75 stw 20,-48(11)
[all …]
/Linux-v5.10/arch/m68k/fpsp040/
Ddo_func.S7 | The opcode and tag bits form an index into a jump table in
101 | Load a signed zero to fp0 and set inex2/ainex
113 | Load a signed zero to fp0; do not set inex2/ainex
121 | Load a signed infinity to fp0; do not set inex2/ainex
129 | Load a signed one to fp0; do not set inex2/ainex
137 | Load a signed pi/2 to fp0; do not set inex2/ainex
145 | Load either a +0 or +inf for plus/minus operand
258 .long smod_snan | 00,11 norm,nan = nan
262 .long smod_snan | 01,11 zero,nan = nan
266 .long smod_snan | 10,11 inf,nan = nan
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/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml16 A hart context is a privilege mode in a hardware execution thread. For example,
21 a pending enabled interrupt and then release it once it has been handled.
23 Each interrupt has a configurable priority. Higher priority interrupts are
24 serviced first. Each context can specify a priority threshold. Interrupts
32 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
34 contains a specific memory layout, which is documented in chapter 8 of the
63 that a context is not present. Each node pointed to should be a
64 riscv,cpu-intc node, which has a riscv node as parent.
90 &cpu0_intc 11
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/Linux-v5.10/arch/mips/include/asm/octeon/
Dcvmx-pow.h15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
19 * You should have received a copy of the GNU General Public License
24 * This file may also be available under a different license from Cavium.
31 * New, starting with SDK 1.7.0, cvmx-pow supports a number of
38 * - Requesting a POW operation with an active tag switch in
40 * - Waiting for a tag switch to complete for an excessively
41 * long period. This is normally a sign of an error in locking
74 /* A tag switch to NULL, and there is no space reserved in POW
77 * - NULL_NULL is entered at the beginning of time and on a deschedule.
78 * - NULL_NULL can be exited by a new work request. A NULL_SWITCH
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/Linux-v5.10/arch/arm64/crypto/
Dsha256-core.S_shipped14 // this file except in compliance with the License. You can obtain a copy
40 // (**) The result is a trade-off: it's possible to improve it by
120 eor w19,w20,w21 // a^b, b^c in next round
121 eor w16,w16,w6,ror#11 // Sigma1(e)
126 and w28,w28,w19 // (b^c)&=(a^b)
128 eor w28,w28,w21 // Maj(a,b,c)
129 eor w17,w6,w17,ror#13 // Sigma0(a)
130 add w27,w27,w28 // h+=Maj(a,b,c)
132 //add w27,w27,w17 // h+=Sigma0(a)
137 add w27,w27,w17 // h+=Sigma0(a)
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Dsha1-ce-core.S12 .arch armv8-a+crypto
101 add_update c, ev, k0, 8, 9, 10, 11, dgb
102 add_update c, od, k0, 9, 10, 11, 8
103 add_update c, ev, k0, 10, 11, 8, 9
104 add_update c, od, k0, 11, 8, 9, 10
105 add_update c, ev, k1, 8, 9, 10, 11
107 add_update p, od, k1, 9, 10, 11, 8
108 add_update p, ev, k1, 10, 11, 8, 9
109 add_update p, od, k1, 11, 8, 9, 10
110 add_update p, ev, k1, 8, 9, 10, 11
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