Lines Matching +full:11 +full:a
16 A hart context is a privilege mode in a hardware execution thread. For example,
21 a pending enabled interrupt and then release it once it has been handled.
23 Each interrupt has a configurable priority. Higher priority interrupts are
24 serviced first. Each context can specify a priority threshold. Interrupts
32 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
34 contains a specific memory layout, which is documented in chapter 8 of the
63 that a context is not present. Each node pointed to should be a
64 riscv,cpu-intc node, which has a riscv node as parent.
90 &cpu0_intc 11
91 &cpu1_intc 11 &cpu1_intc 9
92 &cpu2_intc 11 &cpu2_intc 9
93 &cpu3_intc 11 &cpu3_intc 9
94 &cpu4_intc 11 &cpu4_intc 9>;