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/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_smu.c70 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
72 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
73 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
74 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
75 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ …
76 …ine VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
85 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
86 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ
87 …15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB c…
111 if (delay_us >= 1000) in dcn316_smu_wait_for_response()
[all …]
/Linux-v6.1/drivers/clk/mvebu/
Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
55 [0x0] = 666 * 1000 * 1000,
56 [0x2] = 800 * 1000 * 1000,
57 [0x3] = 800 * 1000 * 1000,
58 [0x4] = 1066 * 1000 * 1000,
59 [0x5] = 1066 * 1000 * 1000,
60 [0x6] = 1200 * 1000 * 1000,
[all …]
Darmada-38x.c23 * 0 = 250 MHz
24 * 1 = 200 MHz
47 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
48 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
49 1332 * 1000 * 1000, 0, 0, 0,
50 1600 * 1000 * 1000, 0, 0, 0,
51 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_smu.c84 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
86 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
87 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
88 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
89 #define VBIOSSMC_MSG_GetDtbclkFreq 0x09 ///< Get display dtb clock frequency in MHZ …
90 …BIOSSMC_MSG_SetDtbClk 0x0A ///< Set dtb clock frequency, return frequemcy in MHZ
92 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x0C ///< To ask PMFW turn off TMDP 48MHz refclk …
99 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
123 if (delay_us >= 1000) in dcn315_smu_wait_for_response()
124 msleep(delay_us/1000); in dcn315_smu_wait_for_response()
[all …]
/Linux-v6.1/drivers/cpufreq/
Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
92 #define SLEEP_FREQ (800 * 1000)
103 unsigned long refresh; /* DRAM refresh counter * 1000 */
125 {0, L0, 1000*1000},
126 {0, L1, 800*1000},
127 {0, L2, 400*1000},
128 {0, L3, 200*1000},
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
[all …]
Dpmac32-cpufreq.c369 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_target()
429 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_resume()
502 * frequency, it claims it to be around 84Mhz on some models while in pmac_cpufreq_init_MacRISC3()
503 * it appears to be approx. 101Mhz on all. Let's hack around here... in pmac_cpufreq_init_MacRISC3()
529 low_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
538 hi_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
586 low_freq = (*value) / 1000; in pmac_cpufreq_init_750FX()
605 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
606 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
607 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
[all …]
Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
119 table[i].frequency = freqs[i].cpufreq_mhz * 1000; in setup_freqs_table()
[all …]
Dimx6q-cpufreq.c67 freq_hz = new_freq * 1000; in imx6q_set_target()
68 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
81 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
82 old_freq / 1000, volt_old / 1000, in imx6q_set_target()
83 new_freq / 1000, volt / 1000); in imx6q_set_target()
122 * CPU may run at higher than 528MHz, this will lead to in imx6q_set_target()
124 * voltage of 528MHz, so lower the CPU frequency to one in imx6q_set_target()
127 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
138 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); in imx6q_set_target()
145 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); in imx6q_set_target()
[all …]
Delanfreq.c45 {1000, 0x02, 0x18},
56 {0, 0, 1000},
72 * at the moment. Frequencies from 1 to 33 MHz are generated
73 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
74 * and have the rest of the chip running with 33 MHz.
89 /* Are we in CPU clock multiplied mode (66/99 MHz)? */ in elanfreq_get_cpu_frequency()
97 /* 33 MHz is not 32 MHz... */ in elanfreq_get_cpu_frequency()
101 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000; in elanfreq_get_cpu_frequency()
117 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) in elanfreq_target()
124 udelay(1000); /* buffers have cleaned up */ in elanfreq_target()
[all …]
Ds3c2416-cpufreq.c98 return clk_get_rate(s3c_freq->armclk) / 1000; in s3c2416_cpufreq_get_speed()
106 if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) { in s3c2416_cpufreq_set_armdiv()
107 ret = clk_set_rate(s3c_freq->armdiv, freq * 1000); in s3c2416_cpufreq_set_armdiv()
131 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_enter_dvs()
191 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
193 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
196 clk_get_rate(s3c_freq->hclk) / 1000, ret); in s3c2416_cpufreq_leave_dvs()
202 clk_get_rate(s3c_freq->armdiv) / 1000); in s3c2416_cpufreq_leave_dvs()
242 ? clk_get_rate(s3c_freq->hclk) / 1000 in s3c2416_cpufreq_set_target()
298 s3c_freq->regulator_latency = 1 * 1000 * 1000; in s3c2416_cpufreq_cfg_regulator()
[all …]
Dspeedstep-centrino.c83 frequency/voltage operating point; frequency in MHz, volts in mV.
85 #define OP(mhz, mv) \ argument
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
98 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
113 OP(1000, 1004),
123 OP(1000, 1164),
135 OP(1000, 1100),
146 OP(1000, 1292),
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c694 pll_settings->reference_freq * 1000, in calculate_ss()
996 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); in dcn31_program_pix_clk()
1161 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1162 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1163 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1164 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1165 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1166 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1167 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
1168 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
[all …]
/Linux-v6.1/arch/arm/mach-s3c/
Dcpu.h77 #define KHZ (1000)
80 #ifndef MHZ
81 #define MHZ (1000*1000) macro
84 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/Linux-v6.1/arch/mips/ralink/
Dmt7620.c64 #define MHZ(x) ((x) * 1000 * 1000) macro
73 return MHZ(40); in mt7620_get_xtal_rate()
75 return MHZ(20); in mt7620_get_xtal_rate()
87 return MHZ(40); in mt7620_get_periph_rate()
104 return MHZ(600); in mt7620_get_cpu_pll_rate()
130 return MHZ(480); in mt7620_get_pll_rate()
205 #define RFRAC(x) (((x) / 1000) % 1000) in ralink_clk_init()
208 if (xtal_rate == MHZ(40)) in ralink_clk_init()
209 cpu_rate = MHZ(580); in ralink_clk_init()
211 cpu_rate = MHZ(575); in ralink_clk_init()
[all …]
/Linux-v6.1/tools/power/cpupower/utils/helpers/
Dmisc.c181 else if (speed > 1000) in print_speed()
182 printf("%u.%03u MHz", ((unsigned int)speed / 1000), in print_speed()
183 (unsigned int)(speed % 1000)); in print_speed()
194 tmp = speed % 1000; in print_speed()
196 speed += 1000; in print_speed()
197 printf("%u MHz", ((unsigned int)speed / 1000)); in print_speed()
198 } else if (speed > 1000) { in print_speed()
202 printf("%u.%01u MHz", ((unsigned int)speed / 1000), in print_speed()
203 ((unsigned int)(speed % 1000) / 100)); in print_speed()
/Linux-v6.1/drivers/clk/
Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/Linux-v6.1/tools/testing/selftests/intel_pstate/
Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
90 min_freq=$(($_min_freq / 1000))
92 max_freq=$(($_max_freq / 1000))
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c483 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
485 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
487 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
489 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
499 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
501 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
503 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
505 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
544 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) in pp_rv_set_hard_min_fclk_by_freq() argument
549 amdgpu_dpm_set_hard_min_fclk_by_freq(adev, mhz); in pp_rv_set_hard_min_fclk_by_freq()
[all …]
/Linux-v6.1/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/Linux-v6.1/Documentation/admin-guide/pm/
Dintel-speed-select.rst154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
434 clos min is not specified, default: 0 MHz
[all …]
/Linux-v6.1/arch/x86/kernel/
Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/Linux-v6.1/drivers/media/dvb-frontends/
Dtda826x.c73 div = (p->frequency + (1000-1)) / 1000; in tda826x_set_params()
75 /* BW = ((1 + RO) * SR/2 + 5) * 1.3 [SR in MSPS, BW in MHz] */ in tda826x_set_params()
77 ksyms = p->symbol_rate / 1000; in tda826x_set_params()
88 buf[2] = (1<<5) | 0x0b; // 1Mhz + 0.45 VCO in tda826x_set_params()
106 priv->frequency = div * 1000; in tda826x_set_params()
121 .frequency_min_hz = 950 * MHz,
122 .frequency_max_hz = 2175 * MHz
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c75 .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */
76 .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */
77 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
78 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
81 .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */
82 .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */
83 .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */
84 .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */
87 .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */
88 .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */
[all …]

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