87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
92 #define SLEEP_FREQ	(800 * 1000)
103 	unsigned long refresh;	/* DRAM refresh counter * 1000 */
125 	{0, L0, 1000*1000},
126 	{0, L1, 800*1000},
127 	{0, L2, 400*1000},
128 	{0, L3, 200*1000},
129 	{0, L4, 100*1000},
175 	/* L0 : [1000/200/100][166/83][133/66][200/200] */
275 		 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287  in s5pv210_target()
294 		 * SCLKA2M(200/1=200)->(200/4=50)Mhz  in s5pv210_target()
308 		 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX  in s5pv210_target()
309 		 * (200/4=50)->(667/4=166)Mhz  in s5pv210_target()
322 		 * 3. DMC1 refresh count for 133Mhz if (index == L4) is  in s5pv210_target()
324 		 * code. 0x287@83Mhz  in s5pv210_target()
375 		/* 5. Set Lock time = 30us*24Mhz = 0x2cf */  in s5pv210_target()
393 		 * 7. Change source clock from SCLKMPLL(667Mhz)  in s5pv210_target()
394 		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX  in s5pv210_target()
395 		 * (667/4=166)->(200/4=50)Mhz  in s5pv210_target()
409 		 * (200/4=50)->(200/1=200)Mhz  in s5pv210_target()
434 		 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c  in s5pv210_target()
435 		 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618  in s5pv210_target()
458 			 * DMC0 : 166Mhz  in s5pv210_target()
459 			 * DMC1 : 200Mhz  in s5pv210_target()
465 			 * DMC0 : 83Mhz  in s5pv210_target()
466 			 * DMC1 : 100Mhz  in s5pv210_target()
537 	s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000);  in s5pv210_cpu_init()
540 	s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000);  in s5pv210_cpu_init()