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/Linux-v6.6/arch/m68k/sun3/
Ddvma.c35 if(ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] != pte) { in dvma_page()
37 ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] = pte; in dvma_page()
61 return 0; in dvma_map_iommu()
67 memset(ptelist, 0, sizeof(ptelist)); in sun3_dvma_init()
/Linux-v6.6/Documentation/devicetree/bindings/media/
Dqcom,msm8916-venus.yaml77 reg = <0x01d00000 0xff000>;
Dqcom,sc7180-venus.yaml103 reg = <0x0aa00000 0xff000>;
115 iommus = <&apps_smmu 0x0c00 0x60>;
Dqcom,sdm845-venus-v2.yaml95 reg = <0x0aa00000 0xff000>;
111 iommus = <&apps_smmu 0x10a0 0x8>,
112 <&apps_smmu 0x10b0 0x0>;
Dqcom,sdm845-venus.yaml105 reg = <0x0aa00000 0xff000>;
112 iommus = <&apps_smmu 0x10a0 0x8>,
113 <&apps_smmu 0x10b0 0x0>;
Dqcom,msm8996-venus.yaml112 reg = <0x00c00000 0xff000>;
120 iommus = <&venus_smmu 0x00>,
121 <&venus_smmu 0x01>,
122 <&venus_smmu 0x0a>,
123 <&venus_smmu 0x07>,
124 <&venus_smmu 0x0e>,
125 <&venus_smmu 0x0f>,
126 <&venus_smmu 0x08>,
127 <&venus_smmu 0x09>,
128 <&venus_smmu 0x0b>,
[all …]
Dqcom,sm8250-venus.yaml113 reg = <0x0aa00000 0xff000>;
129 iommus = <&apps_smmu 0x2100 0x0400>;
Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/Linux-v6.6/arch/s390/kernel/
Dmachine_kexec_reloc.c15 *(u16 *)loc &= 0xf000; in arch_kexec_do_relocs()
16 *(u16 *)loc |= val & 0xfff; in arch_kexec_do_relocs()
22 *(u32 *)loc &= 0xf00000ff; in arch_kexec_do_relocs()
23 *(u32 *)loc |= (val & 0xfff) << 16; /* DL */ in arch_kexec_do_relocs()
24 *(u32 *)loc |= (val & 0xff000) >> 4; /* DH */ in arch_kexec_do_relocs()
55 return 0; in arch_kexec_do_relocs()
Dmodule.c31 #if 0
45 return 0; in get_module_load_offset()
68 NUMA_NO_NODE, __builtin_return_address(0)); in module_alloc()
69 if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) { in module_alloc()
154 for (i = 0; i < hdr->e_shnum; i++) in module_frob_arch_sections()
173 for (i = 0; i < me->arch.nsyms; i++) { in module_frob_arch_sections()
176 "_GLOBAL_OFFSET_TABLE_") == 0) in module_frob_arch_sections()
181 me->arch.syminfo[i].got_initialized = 0; in module_frob_arch_sections()
182 me->arch.syminfo[i].plt_initialized = 0; in module_frob_arch_sections()
186 me->arch.got_size = me->arch.plt_size = 0; in module_frob_arch_sections()
[all …]
/Linux-v6.6/drivers/crypto/bcm/
Dspu2.h14 SPU2_CIPHER_TYPE_NONE = 0x0,
15 SPU2_CIPHER_TYPE_AES128 = 0x1,
16 SPU2_CIPHER_TYPE_AES192 = 0x2,
17 SPU2_CIPHER_TYPE_AES256 = 0x3,
18 SPU2_CIPHER_TYPE_DES = 0x4,
19 SPU2_CIPHER_TYPE_3DES = 0x5,
24 SPU2_CIPHER_MODE_ECB = 0x0,
25 SPU2_CIPHER_MODE_CBC = 0x1,
26 SPU2_CIPHER_MODE_CTR = 0x2,
27 SPU2_CIPHER_MODE_CFB = 0x3,
[all …]
/Linux-v6.6/arch/sparc/include/asm/
Dleon_amba.h24 #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
25 #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
26 #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
27 #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
28 #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
29 #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
30 #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
31 #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
37 #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
38 #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
[all …]
/Linux-v6.6/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_cpt.c16 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD
17 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
24 u64 free_sts = 0, busy_sts = 0; \
28 for (e = (e_min), i = 0; e < (e_max); e++, i++) { \
30 if (reg & 0x1) \
33 if (reg & 0x2) \
50 dev_err_ratelimited(rvu->dev, "Received CPTAF FLT%d irq : 0x%llx", vec, reg); in cpt_af_flt_intr_handler()
55 case 0: in cpt_af_flt_intr_handler()
65 grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF; in cpt_af_flt_intr_handler()
67 rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), 0x0); in cpt_af_flt_intr_handler()
[all …]
/Linux-v6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Ddcore0_tpc0_cfg_masks.h24 #define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0
25 #define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF
28 #define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0
29 #define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF
32 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0
33 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1
36 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0
37 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1
39 #define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10
42 #define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0
[all …]
/Linux-v6.6/arch/riscv/kernel/
Dmodule.c38 return 0; in apply_r_riscv_32_rela()
44 return 0; in apply_r_riscv_64_rela()
51 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
52 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
53 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
54 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
56 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
57 return 0; in apply_r_riscv_branch_rela()
64 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
65 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/Linux-v6.6/sound/soc/sof/intel/
Dbdw.c27 #define BDW_DSP_BAR 0
35 #define IRAM_OFFSET 0xA0000
37 #define DRAM_OFFSET 0x00000
39 #define SHIM_OFFSET 0xFB000
40 #define SHIM_SIZE 0x100
41 #define MBOX_OFFSET 0x9E000
42 #define MBOX_SIZE 0x1000
43 #define MBOX_DUMP_SIZE 0x30
44 #define EXCEPT_OFFSET 0x800
45 #define EXCEPT_MAX_HDR_SIZE 0x400
[all …]
/Linux-v6.6/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c33 #define SVC_GROUP_MASK 0xf
34 #define SVC_NUM_MASK 0xf
38 #define EINT12CON_REG 0x200
39 #define EINT12MASK_REG 0x240
40 #define EINT12PEND_REG 0x260
50 #define SERVICE_REG 0x284
51 #define SERVICEPEND_REG 0x288
53 #define EINT0CON0_REG 0x900
54 #define EINT0MASK_REG 0x920
55 #define EINT0PEND_REG 0x924
[all …]
/Linux-v6.6/arch/powerpc/kvm/
Dbook3s_64_mmu.c24 #define dprintk(X...) do { } while(0)
35 for (i = 0; i < vcpu->arch.slb_nr; i++) { in kvmppc_mmu_book3s_64_find_slbe()
48 dprintk("KVM: No SLB entry found for 0x%lx [%llx | %llx]\n", in kvmppc_mmu_book3s_64_find_slbe()
50 for (i = 0; i < vcpu->arch.slb_nr; i++) { in kvmppc_mmu_book3s_64_find_slbe()
88 return 0; in kvmppc_mmu_book3s_64_ea_to_vp()
126 htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1); in kvmppc_mmu_book3s_64_get_pteg()
137 pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL; in kvmppc_mmu_book3s_64_get_pteg()
140 dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n", in kvmppc_mmu_book3s_64_get_pteg()
180 if ((r & 0xf000) == 0x1000) in decode_pagesize()
184 if ((r & 0xff000) == 0) in decode_pagesize()
[all …]
/Linux-v6.6/arch/powerpc/include/asm/
Dkvm_book3s_64.h40 * 0xFFF0000000000000 12-bit lpid field
41 * 0x000FFFFFFFFFF000 40-bit guest 4k page frame number
42 * 0x0000000000000001 1-bit single entry flag
44 #define RMAP_NESTED_LPID_MASK 0xFFF0000000000000UL
46 #define RMAP_NESTED_GPA_MASK 0x000FFFFFFFFFF000UL
47 #define RMAP_NESTED_IS_SINGLE_ENTRY 0x0000000000000001UL
154 #define HDSISR_CANARY 0x7fff
157 * We use a lock bit in HPTE dword 0 to synchronize updates and
161 #define HPTE_V_HVLOCK 0x40UL
162 #define HPTE_V_ABSENT 0x20UL
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/Linux-v6.6/drivers/iommu/
Dmsm_iommu_hw-8xxx.h39 } while (0)
47 #define FL_BASE_MASK 0xFFFFFC00
48 #define FL_TYPE_TABLE (1 << 0)
49 #define FL_TYPE_SECT (2 << 0)
57 #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
61 #define SL_BASE_MASK_LARGE 0xFFFF0000
62 #define SL_BASE_MASK_SMALL 0xFFFFF000
63 #define SL_TYPE_LARGE (1 << 0)
64 #define SL_TYPE_SMALL (2 << 0)
71 #define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]

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