27 #define BDW_DSP_BAR 0
35 #define IRAM_OFFSET     0xA0000
37 #define DRAM_OFFSET     0x00000
39 #define SHIM_OFFSET     0xFB000
40 #define SHIM_SIZE       0x100
41 #define MBOX_OFFSET     0x9E000
42 #define MBOX_SIZE       0x1000
43 #define MBOX_DUMP_SIZE 0x30
44 #define EXCEPT_OFFSET	0x800
45 #define EXCEPT_MAX_HDR_SIZE	0x400
48 #define DMAC0_OFFSET    0xFE000
49 #define DMAC1_OFFSET    0xFF000
50 #define DMAC_SIZE       0x420
51 #define SSP0_OFFSET     0xFC000
52 #define SSP1_OFFSET     0xFD000
53 #define SSP_SIZE	0x100
57 #define BDW_PANIC_OFFSET(x)	((x) & 0xFFFF)
85 	/* set opportunistic mode on engine 0,1 for all channels */  in bdw_run()
88 				SHIM_HMDC_HDDA_E1_ALLCH, 0);  in bdw_run()
92 					 SHIM_CSR_STALL, 0x0);  in bdw_run()
113 	return 0;  in bdw_reset()
121 	/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */  in bdw_set_dsp_D0()
124 					 PCI_VDRTCL2_DTCGE, 0);  in bdw_set_dsp_D0()
132 					 PCI_PMCS_PS_MASK, 0);  in bdw_set_dsp_D0()
138 		if (reg == 0)  in bdw_set_dsp_D0()
148 	 * select SSP1 19.2MHz base clock, SSP clock 0,  in bdw_set_dsp_D0()
153 					 SHIM_CSR_LPCS, 0x0);  in bdw_set_dsp_D0()
185 					 PCI_VDRTCL2_APLLSE_MASK, 0);  in bdw_set_dsp_D0()
193 					 0xfffffffC, 0x0);  in bdw_set_dsp_D0()
200 	/* set on-demond mode on engine 0,1 for all channels */  in bdw_set_dsp_D0()
209 				(SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);  in bdw_set_dsp_D0()
212 				SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);  in bdw_set_dsp_D0()
215 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);  in bdw_set_dsp_D0()
216 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);  in bdw_set_dsp_D0()
217 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);  in bdw_set_dsp_D0()
218 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);  in bdw_set_dsp_D0()
220 	return 0;  in bdw_set_dsp_D0()
237 		dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",  in bdw_get_registers()
268 		"error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
272 		"error: mask host: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
276 		"error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
280 		"error: mask DSP: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
370 	return 0;  in bdw_send_msg()
392 					 SHIM_IMRX_BUSY, 0);  in bdw_host_done()
399 					 SHIM_IPCX_DONE, 0);  in bdw_dsp_done()
403 					 SHIM_IMRX_DONE, 0);  in bdw_dsp_done()
440 	dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);  in bdw_probe()
444 			"error: failed to ioremap LPE base 0x%x size 0x%x\n",  in bdw_probe()
467 	dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);  in bdw_probe()
471 			"error: failed to ioremap PCI base 0x%x size 0x%x\n",  in bdw_probe()
479 	if (sdev->ipc_irq < 0)  in bdw_probe()
486 	if (ret < 0) {  in bdw_probe()
494 	if (ret < 0) {  in bdw_probe()
501 	if (ret < 0) {  in bdw_probe()
637 	.resindex_lpe_base = 0,
640 	.irqindex_host_ipc = 0,