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/Linux-v5.10/arch/m68k/sun3/
Ddvma.c35 if(ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] != pte) { in dvma_page()
37 ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] = pte; in dvma_page()
61 return 0; in dvma_map_iommu()
67 memset(ptelist, 0, sizeof(ptelist)); in sun3_dvma_init()
/Linux-v5.10/arch/arm/mach-s3c/
Dsleep-s3c24xx.S34 .word 0x2bedf00d
48 mov r2, #S3C24XX_PA_UART & 0xff000000
49 orr r2, r2, #S3C24XX_PA_UART & 0xff000
51 #if 0
54 ldr r12, [ r14, #0x54 ]
57 str r12, [ r14, #0x54 ]
/Linux-v5.10/arch/s390/kernel/
Dmachine_kexec_reloc.c15 *(u16 *)loc &= 0xf000; in arch_kexec_do_relocs()
16 *(u16 *)loc |= val & 0xfff; in arch_kexec_do_relocs()
22 *(u32 *)loc &= 0xf00000ff; in arch_kexec_do_relocs()
23 *(u32 *)loc |= (val & 0xfff) << 16; /* DL */ in arch_kexec_do_relocs()
24 *(u32 *)loc |= (val & 0xff000) >> 4; /* DH */ in arch_kexec_do_relocs()
55 return 0; in arch_kexec_do_relocs()
Dmodule.c27 #if 0
42 GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, in module_alloc()
43 __builtin_return_address(0)); in module_alloc()
44 if (p && (kasan_module_alloc(p, size) < 0)) { in module_alloc()
121 for (i = 0; i < hdr->e_shnum; i++) in module_frob_arch_sections()
140 for (i = 0; i < me->arch.nsyms; i++) { in module_frob_arch_sections()
143 "_GLOBAL_OFFSET_TABLE_") == 0) in module_frob_arch_sections()
148 me->arch.syminfo[i].got_initialized = 0; in module_frob_arch_sections()
149 me->arch.syminfo[i].plt_initialized = 0; in module_frob_arch_sections()
153 me->arch.got_size = me->arch.plt_size = 0; in module_frob_arch_sections()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/media/
Dqcom,msm8916-venus.yaml104 reg = <0x01d00000 0xff000>;
Dqcom,sdm845-venus-v2.yaml119 reg = <0x0aa00000 0xff000>;
135 iommus = <&apps_smmu 0x10a0 0x8>,
136 <&apps_smmu 0x10b0 0x0>;
Dqcom,sdm845-venus.yaml132 reg = <0x0aa00000 0xff000>;
139 iommus = <&apps_smmu 0x10a0 0x8>,
140 <&apps_smmu 0x10b0 0x0>;
Dqcom,sc7180-venus.yaml124 reg = <0x0aa00000 0xff000>;
136 iommus = <&apps_smmu 0x0c00 0x60>;
Dqcom,msm8996-venus.yaml131 reg = <0x00c00000 0xff000>;
139 iommus = <&venus_smmu 0x00>,
140 <&venus_smmu 0x01>,
141 <&venus_smmu 0x0a>,
142 <&venus_smmu 0x07>,
143 <&venus_smmu 0x0e>,
144 <&venus_smmu 0x0f>,
145 <&venus_smmu 0x08>,
146 <&venus_smmu 0x09>,
147 <&venus_smmu 0x0b>,
[all …]
/Linux-v5.10/drivers/crypto/bcm/
Dspu2.h14 SPU2_CIPHER_TYPE_NONE = 0x0,
15 SPU2_CIPHER_TYPE_AES128 = 0x1,
16 SPU2_CIPHER_TYPE_AES192 = 0x2,
17 SPU2_CIPHER_TYPE_AES256 = 0x3,
18 SPU2_CIPHER_TYPE_DES = 0x4,
19 SPU2_CIPHER_TYPE_3DES = 0x5,
24 SPU2_CIPHER_MODE_ECB = 0x0,
25 SPU2_CIPHER_MODE_CBC = 0x1,
26 SPU2_CIPHER_MODE_CTR = 0x2,
27 SPU2_CIPHER_MODE_CFB = 0x3,
[all …]
/Linux-v5.10/arch/sparc/include/asm/
Dleon_amba.h24 #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
25 #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
26 #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
27 #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
28 #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
29 #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
30 #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
31 #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
37 #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
38 #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
[all …]
/Linux-v5.10/arch/riscv/kernel/
Dmodule.c24 return 0; in apply_r_riscv_32_rela()
30 return 0; in apply_r_riscv_64_rela()
37 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
38 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
39 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
40 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
42 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
43 return 0; in apply_r_riscv_branch_rela()
50 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
51 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/Linux-v5.10/sound/soc/sof/intel/
Dbdw.c23 #define BDW_DSP_BAR 0
31 #define IRAM_OFFSET 0xA0000
33 #define DRAM_OFFSET 0x00000
35 #define SHIM_OFFSET 0xFB000
36 #define SHIM_SIZE 0x100
37 #define MBOX_OFFSET 0x9E000
38 #define MBOX_SIZE 0x1000
39 #define MBOX_DUMP_SIZE 0x30
40 #define EXCEPT_OFFSET 0x800
41 #define EXCEPT_MAX_HDR_SIZE 0x400
[all …]
/Linux-v5.10/drivers/thermal/qcom/
Dtsens-v0_1.c10 #define SROT_CTRL_OFF 0x0000
13 #define TM_INT_EN_OFF 0x0000
14 #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15 #define TM_Sn_STATUS_OFF 0x0030
16 #define TM_TRDY_OFF 0x005c
19 #define MSM8916_BASE0_MASK 0x0000007f
20 #define MSM8916_BASE1_MASK 0xfe000000
21 #define MSM8916_BASE0_SHIFT 0
24 #define MSM8916_S0_P1_MASK 0x00000f80
25 #define MSM8916_S1_P1_MASK 0x003e0000
[all …]
/Linux-v5.10/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c33 #define SVC_GROUP_MASK 0xf
34 #define SVC_NUM_MASK 0xf
38 #define EINT12CON_REG 0x200
39 #define EINT12MASK_REG 0x240
40 #define EINT12PEND_REG 0x260
50 #define SERVICE_REG 0x284
51 #define SERVICEPEND_REG 0x288
53 #define EINT0CON0_REG 0x900
54 #define EINT0MASK_REG 0x920
55 #define EINT0PEND_REG 0x924
[all …]
/Linux-v5.10/arch/powerpc/kvm/
Dbook3s_64_mmu.c24 #define dprintk(X...) do { } while(0)
35 for (i = 0; i < vcpu->arch.slb_nr; i++) { in kvmppc_mmu_book3s_64_find_slbe()
48 dprintk("KVM: No SLB entry found for 0x%lx [%llx | %llx]\n", in kvmppc_mmu_book3s_64_find_slbe()
50 for (i = 0; i < vcpu->arch.slb_nr; i++) { in kvmppc_mmu_book3s_64_find_slbe()
88 return 0; in kvmppc_mmu_book3s_64_ea_to_vp()
126 htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1); in kvmppc_mmu_book3s_64_get_pteg()
137 pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL; in kvmppc_mmu_book3s_64_get_pteg()
140 dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n", in kvmppc_mmu_book3s_64_get_pteg()
180 if ((r & 0xf000) == 0x1000) in decode_pagesize()
184 if ((r & 0xff000) == 0) in decode_pagesize()
[all …]
/Linux-v5.10/arch/powerpc/include/asm/
Dkvm_book3s_64.h53 * 0xFFF0000000000000 12-bit lpid field
54 * 0x000FFFFFFFFFF000 40-bit guest 4k page frame number
55 * 0x0000000000000001 1-bit single entry flag
57 #define RMAP_NESTED_LPID_MASK 0xFFF0000000000000UL
59 #define RMAP_NESTED_GPA_MASK 0x000FFFFFFFFFF000UL
60 #define RMAP_NESTED_IS_SINGLE_ENTRY 0x0000000000000001UL
160 * We use a lock bit in HPTE dword 0 to synchronize updates and
164 #define HPTE_V_HVLOCK 0x40UL
165 #define HPTE_V_ABSENT 0x20UL
189 asm volatile(" ldarx %0,0,%2\n" in try_lock_hpte()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/Linux-v5.10/drivers/iommu/
Dmsm_iommu_hw-8xxx.h39 } while (0)
47 #define FL_BASE_MASK 0xFFFFFC00
48 #define FL_TYPE_TABLE (1 << 0)
49 #define FL_TYPE_SECT (2 << 0)
57 #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
61 #define SL_BASE_MASK_LARGE 0xFFFF0000
62 #define SL_BASE_MASK_SMALL 0xFFFFF000
63 #define SL_TYPE_LARGE (1 << 0)
64 #define SL_TYPE_SMALL (2 << 0)
71 #define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dmsm8916.dtsi30 reg = <0 0 0 0>;
39 reg = <0x0 0x86000000 0x0 0x300000>;
44 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 reg = <0x0 0x89300000 0x0 0x600000>;
[all …]
/Linux-v5.10/sound/pci/cs46xx/
Ddsp_spos.c48 unsigned int i = 0, j, nreallocated = 0; in shadow_and_reallocate_code()
60 if (ins->code.offset > 0) { in shadow_and_reallocate_code()
61 mop_operands = (hival >> 6) & 0x03fff; in shadow_and_reallocate_code()
65 if (mop_type == 0 && in shadow_and_reallocate_code()
66 (mop_operands & WIDE_LADD_INSTR_MASK) == 0 && in shadow_and_reallocate_code()
67 (mop_operands & WIDE_INSTR_MASK) != 0) { in shadow_and_reallocate_code()
68 wide_op = loval & 0x7f; in shadow_and_reallocate_code()
69 for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) { in shadow_and_reallocate_code()
72 address = (hival & 0x00FFF) << 5; in shadow_and_reallocate_code()
79 if ( !(address & 0x8000) ) { in shadow_and_reallocate_code()
[all …]

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