Searched +full:0 +full:xfc030000 (Results 1 – 5 of 5) sorted by relevance
86 reg = <0xfc030000 0x100>;96 … dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
24 #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */25 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */26 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */27 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */28 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */29 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */30 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */31 #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */32 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */33 #define MCFINTC_ICR0 0x40 /* Base ICR register */[all …]
40 #define MCF_WTM_WCR 0xFC09800045 #define MCFSIM_IPRL 0xFC04800446 #define MCFSIM_IPRH 0xFC04800048 #define MCFSIM_IMRL 0xFC04800C49 #define MCFSIM_IMRH 0xFC04800851 #define MCFSIM_ICR0 0xFC048040 52 #define MCFSIM_ICR1 0xFC048041 53 #define MCFSIM_ICR2 0xFC048042 54 #define MCFSIM_ICR3 0xFC048043 55 #define MCFSIM_ICR4 0xFC048044 [all …]
28 #size-cells = <0>;30 cpu@0 {33 reg = <0>;40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;45 reg = <0x740000 0x1000>;61 reg = <0x73c000 0x1000>;77 reg = <0x20000000 0x20000000>;83 #clock-cells = <0>;84 clock-frequency = <0>;89 #clock-cells = <0>;[all …]
46 #size-cells = <0>;48 cpu@0 {51 reg = <0>;58 reg = <0x20000000 0x20000000>;64 #clock-cells = <0>;65 clock-frequency = <0>;70 #clock-cells = <0>;71 clock-frequency = <0>;76 #clock-cells = <0>;83 reg = <0x00210000 0x10000>;[all …]
