Lines Matching +full:0 +full:xfc030000
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
45 reg = <0x740000 0x1000>;
61 reg = <0x73c000 0x1000>;
77 reg = <0x20000000 0x20000000>;
83 #clock-cells = <0>;
84 clock-frequency = <0>;
89 #clock-cells = <0>;
90 clock-frequency = <0>;
96 reg = <0x00200000 0x20000>;
99 ranges = <0 0x00200000 0x20000>;
111 reg = <0x00100000 0x2400>;
114 ranges = <0 0x00100000 0x2400>;
120 reg = <0x00300000 0x100000
121 0xfc02c000 0x400>;
130 reg = <0x00400000 0x100000>;
139 reg = <0x00500000 0x100000>;
148 reg = <0x00a00000 0x1000>;
159 reg = <0x10000000 0x10000000
160 0x60000000 0x30000000>;
161 ranges = <0x0 0x0 0x10000000 0x10000000
162 0x1 0x0 0x60000000 0x10000000
163 0x2 0x0 0x70000000 0x10000000
164 0x3 0x0 0x80000000 0x10000000>;
182 reg = <0xa0000000 0x300>;
183 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
193 reg = <0xb0000000 0x300>;
194 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
204 reg = <0xc0000000 0x8000000>;
215 reg = <0xf0000000 0x2000>;
216 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
224 #size-cells = <0>;
226 port@0 {
228 #size-cells = <0>;
229 reg = <0>;
241 reg = <0xf0008000 0x4000>;
245 #clock-cells = <0>;
252 reg = <0xf000c000 0x200>;
259 reg = <0xf0010000 0x1000>;
260 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
269 reg = <0xf0004000 0x1000>;
270 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
278 reg = <0xf0014000 0x160>;
287 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
292 #size-cells = <0>;
298 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
303 #size-cells = <0>;
309 reg = <0xf0028000 0x100>;
310 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
312 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
322 reg = <0xf002c000 0x100>;
323 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
338 reg = <0xf8000000 0x100>;
341 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
344 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
351 #size-cells = <0>;
357 reg = <0xf8004000 0x4000>;
360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
363 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
373 reg = <0xf8008000 0x1000>;
374 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
378 #size-cells = <0>;
387 #size-cells = <0>;
388 reg = <0xf800c000 0x100>;
389 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
397 #size-cells = <0>;
398 reg = <0xf8010000 0x100>;
399 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
406 reg = <0xf8014000 0x1000>;
415 reg = <0xf8014070 0x490>,
416 <0xf8014500 0x100>;
422 reg = <0xf8018000 0x124>;
425 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
435 reg = <0xf801c000 0x100>;
438 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
441 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
451 reg = <0xf8020000 0x100>;
454 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
467 reg = <0xf8024000 0x100>;
470 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
473 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
483 reg = <0xf8028000 0x100>;
486 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
487 AT91_XDMAC_DT_PERID(0))>,
489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
493 #size-cells = <0>;
501 reg = <0xf802c000 0x4000>;
510 reg = <0xf8030000 0x98>;
515 reg = <0xf8034000 0x200>;
519 ranges = <0x0 0xf8034000 0x800>;
524 reg = <0x200 0x200>;
529 (AT91_XDMAC_DT_MEM_IF(0) |
533 (AT91_XDMAC_DT_MEM_IF(0) |
543 reg = <0x400 0x200>;
546 #size-cells = <0>;
550 (AT91_XDMAC_DT_MEM_IF(0) |
554 (AT91_XDMAC_DT_MEM_IF(0) |
564 reg = <0x600 0x200>;
567 #size-cells = <0>;
570 (AT91_XDMAC_DT_MEM_IF(0) |
574 (AT91_XDMAC_DT_MEM_IF(0) |
585 reg = <0xf8038000 0x200>;
589 ranges = <0x0 0xf8038000 0x800>;
594 reg = <0x200 0x200>;
599 (AT91_XDMAC_DT_MEM_IF(0) |
603 (AT91_XDMAC_DT_MEM_IF(0) |
613 reg = <0x400 0x200>;
616 #size-cells = <0>;
620 (AT91_XDMAC_DT_MEM_IF(0) |
624 (AT91_XDMAC_DT_MEM_IF(0) |
634 reg = <0x600 0x200>;
637 #size-cells = <0>;
640 (AT91_XDMAC_DT_MEM_IF(0) |
644 (AT91_XDMAC_DT_MEM_IF(0) |
655 reg = <0xf8044000 0x1420>;
660 ranges = <0 0xf8044000 0x1420>;
665 reg = <0xf8048000 0x10>;
671 reg = <0xf8048010 0x10>;
674 #size-cells = <0>;
680 reg = <0xf8048030 0x10>;
687 reg = <0xf8048040 0x10>;
695 reg = <0xf8048050 0x4>;
698 #clock-cells = <0>;
703 reg = <0xf80480b0 0x30>;
710 reg = <0xf8050000 0x100>;
713 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
716 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
728 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
738 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
744 reg = <0xfc000000 0x100>;
747 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
750 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
757 #size-cells = <0>;
763 reg = <0xfc008000 0x100>;
766 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
769 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
779 reg = <0xfc00c000 0x100>;
781 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
784 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
795 reg = <0xfc010000 0x200>;
799 ranges = <0x0 0xfc010000 0x800>;
804 reg = <0x200 0x200>;
809 (AT91_XDMAC_DT_MEM_IF(0) |
813 (AT91_XDMAC_DT_MEM_IF(0) |
823 reg = <0x400 0x200>;
826 #size-cells = <0>;
830 (AT91_XDMAC_DT_MEM_IF(0) |
834 (AT91_XDMAC_DT_MEM_IF(0) |
844 reg = <0x600 0x200>;
847 #size-cells = <0>;
850 (AT91_XDMAC_DT_MEM_IF(0) |
854 (AT91_XDMAC_DT_MEM_IF(0) |
865 reg = <0xfc014000 0x200>;
869 ranges = <0x0 0xfc014000 0x800>;
874 reg = <0x200 0x200>;
879 (AT91_XDMAC_DT_MEM_IF(0) |
883 (AT91_XDMAC_DT_MEM_IF(0) |
893 reg = <0x400 0x200>;
896 #size-cells = <0>;
900 (AT91_XDMAC_DT_MEM_IF(0) |
904 (AT91_XDMAC_DT_MEM_IF(0) |
914 reg = <0x600 0x200>;
917 #size-cells = <0>;
920 (AT91_XDMAC_DT_MEM_IF(0) |
924 (AT91_XDMAC_DT_MEM_IF(0) |
936 reg = <0xfc018000 0x200>;
940 ranges = <0x0 0xfc018000 0x800>;
945 reg = <0x200 0x200>;
950 (AT91_XDMAC_DT_MEM_IF(0) |
954 (AT91_XDMAC_DT_MEM_IF(0) |
964 reg = <0x400 0x200>;
967 #size-cells = <0>;
971 (AT91_XDMAC_DT_MEM_IF(0) |
975 (AT91_XDMAC_DT_MEM_IF(0) |
985 reg = <0x600 0x200>;
988 #size-cells = <0>;
991 (AT91_XDMAC_DT_MEM_IF(0) |
995 (AT91_XDMAC_DT_MEM_IF(0) |
1006 reg = <0xfc01c000 0x100>;
1007 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1015 reg = <0xfc020000 0x200>;
1021 reg = <0xfc028000 0x100>;
1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1027 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1031 #size-cells = <0>;
1039 reg = <0xfc030000 0x100>;
1043 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1065 reg = <0xfc038000 0x600>;
1079 reg = <0xfc040000 0x100>;
1087 reg = <0xfc044000 0x100>;
1088 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1090 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1093 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1103 reg = <0xfc048000 0x100>;
1106 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1116 reg = <0xfc04c000 0x100>;
1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1122 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1134 reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
1144 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
1150 reg = <0xfc05c000 0x20>;
1155 reg = <0xfc069000 0x8>;