| /Linux-v5.4/arch/powerpc/kvm/ |
| D | book3s_xive_template.c | 14 static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc) in GLUE()
38 cppr = ack & 0xff; in GLUE()
40 xc->pending |= 1 << cppr; in GLUE()
44 if (cppr >= xc->hw_cppr) in GLUE()
46 smp_processor_id(), cppr, xc->hw_cppr); in GLUE()
51 * xc->cppr, this will be done as we scan for interrupts in GLUE()
54 xc->hw_cppr = cppr; in GLUE()
76 __x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in GLUE()
102 __x_writeq(0, __x_trig_page(xd)); in GLUE()
112 static u32 GLUE(X_PFX,scan_interrupts)(struct kvmppc_xive_vcpu *xc, in GLUE()
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| D | book3s_xive.c | 91 vcpu->arch.irq_pending = 0; in kvmppc_xive_push_vcpu()
124 /* Now P is 0, we can clear the flag */ in kvmppc_xive_push_vcpu()
125 vcpu->arch.xive_esc_on = 0; in kvmppc_xive_push_vcpu()
144 out_be64(xd->trig_mmio, 0); in xive_irq_trigger()
178 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in kvmppc_xive_attach_escalation() local
179 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_attach_escalation()
184 if (xc->esc_virq[prio]) in kvmppc_xive_attach_escalation()
185 return 0; in kvmppc_xive_attach_escalation()
188 xc->esc_virq[prio] = irq_create_mapping(NULL, q->esc_irq); in kvmppc_xive_attach_escalation()
189 if (!xc->esc_virq[prio]) { in kvmppc_xive_attach_escalation()
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| D | book3s_xive_native.c | 43 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in kvmppc_xive_native_cleanup_queue() local
44 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_native_cleanup_queue()
46 xive_native_disable_queue(xc->vp_id, q, prio); in kvmppc_xive_native_cleanup_queue()
55 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in kvmppc_xive_native_cleanup_vcpu() local
61 if (!xc) in kvmppc_xive_native_cleanup_vcpu()
64 pr_devel("native_cleanup_vcpu(cpu=%d)\n", xc->server_num); in kvmppc_xive_native_cleanup_vcpu()
67 xc->valid = false; in kvmppc_xive_native_cleanup_vcpu()
71 for (i = 0; i < KVMPPC_XIVE_Q_COUNT; i++) { in kvmppc_xive_native_cleanup_vcpu()
73 if (xc->esc_virq[i]) { in kvmppc_xive_native_cleanup_vcpu()
74 if (xc->xive->single_escalation) in kvmppc_xive_native_cleanup_vcpu()
[all …]
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| /Linux-v5.4/drivers/block/paride/ |
| D | fit3.c | 32 #define j44(a,b) (((a>>3)&0x0f)|((b<<1)&0xf0))
35 #define r7() (in_p(7) & 0xff)
37 /* cont = 0 - access the IDE register file
48 case 0: in fit3_write_regr()
49 case 1: w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
50 w0(val); w2(0xd); in fit3_write_regr()
51 w0(0); w2(0xc); in fit3_write_regr()
54 case 2: w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
55 w4(val); w4(0); in fit3_write_regr()
56 w2(0xc); in fit3_write_regr()
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| /Linux-v5.4/arch/s390/lib/ |
| D | xor.c | 18 " aghi %0,-1\n" in xor_xc_2()
20 " srlg 0,%0,8\n" in xor_xc_2()
21 " ltgr 0,0\n" in xor_xc_2()
23 "0: xc 0(256,%1),0(%2)\n" in xor_xc_2()
26 " brctg 0,0b\n" in xor_xc_2()
27 "1: ex %0,0(1)\n" in xor_xc_2()
29 "2: xc 0(1,%1),0(%2)\n" in xor_xc_2()
32 : "0", "1", "cc", "memory"); in xor_xc_2()
40 " aghi %0,-1\n" in xor_xc_3()
42 " srlg 0,%0,8\n" in xor_xc_3()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/thm/ |
| D | thm_9_0_sh_mask.h | 27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
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| D | thm_10_0_sh_mask.h | 27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
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| /Linux-v5.4/arch/powerpc/sysdev/xive/ |
| D | common.c | 42 #define DBG_VERBOSE(fmt...) do { } while(0)
75 #define XIVE_BAD_IRQ 0x7fffffff
83 * or 0 if there is no new entry.
92 return 0; in xive_read_eq()
97 return 0; in xive_read_eq()
105 if (q->idx == 0) in xive_read_eq()
109 return cur & 0x7fffffff; in xive_read_eq()
119 * (0xff if none) and return what was found (0 if none).
135 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) in xive_scan_interrupts() argument
137 u32 irq = 0; in xive_scan_interrupts()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| D | mmhub_9_4_1_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
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| D | mmhub_1_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
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| D | mmhub_9_3_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
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| D | mmhub_9_1_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
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| D | mmhub_2_0_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_2_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
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| D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| D | uvd_6_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
| D | dcn_2_0_0_sh_mask.h | 27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
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| D | dpcs_2_1_0_sh_mask.h | 27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
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| D | dcn_2_1_0_sh_mask.h | 27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
38 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
39 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | imx7ulp-pinfunc.h | 15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
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| /Linux-v5.4/arch/mips/math-emu/ |
| D | ieee754int.h | 18 MADDF_NEGATE_PRODUCT = 1 << 0,
23 ieee754_csr.cx = 0; in ieee754_clearcx()
39 static inline int ieee754_class_nan(int xc) in ieee754_class_nan() argument
41 return xc >= IEEE754_CLASS_SNAN; in ieee754_class_nan()
45 unsigned int xm; int xe; int xs __maybe_unused; int xc
59 if (vm == 0) \
77 #define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm)
83 u64 xm; int xe; int xs __maybe_unused; int xc
97 if (vm == 0) \
115 #define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm)
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_7_1_3_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
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| /Linux-v5.4/tools/perf/pmu-events/arch/x86/bonnell/ |
| D | virtual-memory.json | 3 "EventCode": "0x8",
4 "Counter": "0,1",
5 "UMask": "0x7",
11 "EventCode": "0x8",
12 "Counter": "0,1",
13 "UMask": "0x5",
19 "EventCode": "0x8",
20 "Counter": "0,1",
21 "UMask": "0x9",
27 "EventCode": "0x8",
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_8_2_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| D | nbio_7_0_sh_mask.h | 27 …FG0_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0
28 …NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
30 …FG0_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0
31 …NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
33 …FG0_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
34 …FG0_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
35 …FG0_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
36 …NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
37 …NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
38 …NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
[all …]
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