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/Linux-v5.10/lib/
Dtest_xarray.c20 void xa_dump(const struct xarray *xa) { } in xa_dump() argument
23 #define XA_BUG_ON(xa, x) do { \ argument
27 xa_dump(xa); \
32 } while (0)
40 static void *xa_store_index(struct xarray *xa, unsigned long index, gfp_t gfp) in xa_store_index() argument
42 return xa_store(xa, index, xa_mk_index(index), gfp); in xa_store_index()
45 static void xa_insert_index(struct xarray *xa, unsigned long index) in xa_insert_index() argument
47 XA_BUG_ON(xa, xa_insert(xa, index, xa_mk_index(index), in xa_insert_index()
48 GFP_KERNEL) != 0); in xa_insert_index()
51 static void xa_alloc_index(struct xarray *xa, unsigned long index, gfp_t gfp) in xa_alloc_index() argument
[all …]
Dxarray.c18 * @xa is used to refer to the entire xarray.
31 static inline unsigned int xa_lock_type(const struct xarray *xa) in xa_lock_type() argument
33 return (__force unsigned int)xa->xa_flags & 3; in xa_lock_type()
56 static inline bool xa_track_free(const struct xarray *xa) in xa_track_free() argument
58 return xa->xa_flags & XA_FLAGS_TRACK_FREE; in xa_track_free()
61 static inline bool xa_zero_busy(const struct xarray *xa) in xa_zero_busy() argument
63 return xa->xa_flags & XA_FLAGS_ZERO_BUSY; in xa_zero_busy()
66 static inline void xa_mark_set(struct xarray *xa, xa_mark_t mark) in xa_mark_set() argument
68 if (!(xa->xa_flags & XA_FLAGS_MARK(mark))) in xa_mark_set()
69 xa->xa_flags |= XA_FLAGS_MARK(mark); in xa_mark_set()
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/Linux-v5.10/include/linux/
Dxarray.h34 * 0-62: Sibling entries
54 WARN_ON((long)v < 0); in xa_mk_value()
85 * @tag: Tag value (0, 1 or 3).
88 * of storing value entries. Three tags are available (0, 1 and 3).
134 * Internal entries are used for a number of purposes. Entries 0-255 are
135 * used for sibling entries (only 0-62 are used by the current code). 256
211 * the errno from the pointer value, or returns 0 if the pointer does not
215 * Return: A negative errno or 0.
222 return 0; in xa_err()
233 * * xa_limit_32b - [0 - UINT_MAX]
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/Linux-v5.10/net/core/
Dxdp.c22 #define REG_STATE_NEW 0x0
23 #define REG_STATE_REGISTERED 0x1
24 #define REG_STATE_UNREGISTERED 0x2
25 #define REG_STATE_UNUSED 0x3
29 #define MEM_ID_MAX 0xFFFE
51 const struct xdp_mem_allocator *xa = ptr; in xdp_mem_id_cmp() local
54 return xa->mem.id != mem_id; in xdp_mem_id_cmp()
71 struct xdp_mem_allocator *xa; in __xdp_mem_allocator_rcu_free() local
73 xa = container_of(rcu, struct xdp_mem_allocator, rcu); in __xdp_mem_allocator_rcu_free()
76 ida_simple_remove(&mem_id_pool, xa->mem.id); in __xdp_mem_allocator_rcu_free()
[all …]
/Linux-v5.10/tools/testing/radix-tree/
Dmultiorder.c15 static int item_insert_order(struct xarray *xa, unsigned long index, in item_insert_order() argument
18 XA_STATE_ORDER(xas, xa, index, order); in item_insert_order()
28 return 0; in item_insert_order()
34 void multiorder_iteration(struct xarray *xa) in multiorder_iteration() argument
36 XA_STATE(xas, xa, 0); in multiorder_iteration()
41 int index[NUM_ENTRIES] = {0, 2, 4, 8, 16, 32, 34, 36, 64, 72, 128}; in multiorder_iteration()
42 int order[NUM_ENTRIES] = {1, 1, 2, 3, 4, 1, 0, 1, 3, 0, 7}; in multiorder_iteration()
46 for (i = 0; i < NUM_ENTRIES; i++) { in multiorder_iteration()
47 err = item_insert_order(xa, index[i], order[i]); in multiorder_iteration()
51 for (j = 0; j < 256; j++) { in multiorder_iteration()
[all …]
Diteration_check_2.c15 XA_STATE(xas, arg, 0); in iterator()
21 xas_set(&xas, 0); in iterator()
35 struct xarray *xa = arg; in throbber() local
42 for (i = 0; i < 100; i++) { in throbber()
43 xa_store(xa, i, xa_mk_value(i), GFP_KERNEL); in throbber()
44 xa_set_mark(xa, i, XA_MARK_0); in throbber()
46 for (i = 0; i < 100; i++) in throbber()
47 xa_erase(xa, i); in throbber()
67 if (pthread_create(&threads[0], NULL, iterator, &array)) { in iteration_test2()
79 for (i = 0; i < 2; i++) { in iteration_test2()
/Linux-v5.10/drivers/infiniband/core/
Drestrack.c21 * Return: 0 on success
34 for (i = 0; i < RDMA_RESTRACK_MAX; i++) in rdma_restrack_init()
35 xa_init_flags(&rt[i].xa, XA_FLAGS_ALLOC); in rdma_restrack_init()
37 return 0; in rdma_restrack_init()
68 for (i = 0 ; i < RDMA_RESTRACK_MAX; i++) { in rdma_restrack_clean()
69 struct xarray *xa = &dev->res[i].xa; in rdma_restrack_clean() local
71 if (!xa_empty(xa)) { in rdma_restrack_clean()
78 xa_for_each(xa, index, e) { in rdma_restrack_clean()
98 xa_destroy(xa); in rdma_restrack_clean()
115 XA_STATE(xas, &rt->xa, 0); in rdma_restrack_count()
[all …]
/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb/
Dvsc7326_reg.h14 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
17 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
18 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
19 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
20 #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
21 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
22 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
23 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
24 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
25 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
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/Linux-v5.10/include/trace/events/
Dxdp.h92 ((struct _bpf_dtab_netdev *)tgt)->dev->ifindex : 0)
120 __entry->map_id = map ? map->id : 0;
121 __entry->map_index = map ? index : 0;
149 trace_xdp_redirect(dev, xdp, NULL, 0, NULL, to);
155 trace_xdp_redirect(dev, xdp, to, 0, map, index);
305 __MEM_TYPE_MAP(__MEM_TYPE_SYM_FN) { -1, 0 }
310 TP_PROTO(const struct xdp_mem_allocator *xa),
312 TP_ARGS(xa),
315 __field(const struct xdp_mem_allocator *, xa)
322 __entry->xa = xa;
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/Linux-v5.10/arch/arm/boot/dts/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]
Dgc_9_0_sh_mask.h25 …DC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
26 …DC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
27 …DC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
28 …DC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
29 …DC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
30 …DC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
31 …DC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
32 …DC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
33 …C_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
34 …C_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
[all …]
Dgc_10_1_0_sh_mask.h27 …DEC_START__START__SHIFT 0x0
28 …T__START_MASK 0xFFFFFFFFL
30 …PG_CNTL__CMD__SHIFT 0x0
31 …G_CNTL__STATUS__SHIFT 0x10
32 …_CMD_MASK 0x0000000FL
33 …_STATUS_MASK 0x000F0000L
35 …PG_CTX_LO__ADDR__SHIFT 0x0
36 …O__ADDR_MASK 0xFFFFFFFFL
38 …PG_CTX_HI__ADDR__SHIFT 0x0
39 …I__ADDR_MASK 0xFFFFFFFFL
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/Linux-v5.10/crypto/
Ddh.c19 MPI xa; /* Value is guaranteed to be set. */ member
27 mpi_free(ctx->xa); in dh_clear_ctx()
28 memset(ctx, 0, sizeof(*ctx)); in dh_clear_ctx()
33 * ya = g^xa mod p; [RFC2631 sec 2.1.1]
35 * ZZ = yb^xa mod p; [RFC2631 sec 2.1.1]
39 /* val = base^xa mod p */ in _compute_val()
40 return mpi_powm(val, base, ctx->xa, ctx->p); in _compute_val()
50 return (p_len < 1536) ? -EINVAL : 0; in dh_check_params_length()
72 return 0; in dh_set_params()
84 if (crypto_dh_decode_key(buf, len, &params) < 0) in dh_set_secret()
[all …]
/Linux-v5.10/drivers/iommu/
Dioasid.c45 * @xa: xarray holds the IOASID space
52 #define IOASID_ALLOCATOR_CUSTOM BIT(0) /* Needs framework to track results */
54 struct xarray xa; member
71 .flags = 0,
72 .xa = XARRAY_INIT(ioasid_xa, XA_FLAGS_ALLOC),
81 if (xa_alloc(&default_allocator.xa, &id, opaque, XA_LIMIT(min, max), GFP_ATOMIC)) { in default_alloc()
93 ioasid_data = xa_erase(&default_allocator.xa, ioasid); in default_free()
106 xa_init_flags(&ia_data->xa, XA_FLAGS_ALLOC); in ioasid_alloc_allocator()
128 * are managed by IOASID framework similar to data stored in xa by default
142 int ret = 0; in ioasid_register_allocator()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/Linux-v5.10/drivers/block/paride/
Dktti.c24 #define j44(a,b) (((a>>4)&0x0f)|(b&0xf0))
26 /* cont = 0 - access the IDE register file
30 static int cont_map[2] = { 0x10, 0x08 };
38 w0(r); w2(0xb); w2(0xa); w2(3); w2(6); in ktti_write_regr()
39 w0(val); w2(3); w0(0); w2(6); w2(0xb); in ktti_write_regr()
48 w0(r); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_regr()
49 a = r1(); w2(0xc); b = r1(); w2(9); w2(0xc); w2(9); in ktti_read_regr()
58 for (k=0;k<count/2;k++) { in ktti_read_block()
59 w0(0x10); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_block()
60 a = r1(); w2(0xc); b = r1(); w2(9); in ktti_read_block()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h28 DC_IH_SRC_ID_START = 0x1,
29 DC_IH_SRC_ID_END = 0x1f,
30 VGA_IH_SRC_ID_START = 0x20,
31 VGA_IH_SRC_ID_END = 0x27,
32 CAP_IH_SRC_ID_START = 0x28,
33 CAP_IH_SRC_ID_END = 0x2f,
34 VIP_IH_SRC_ID_START = 0x30,
35 VIP_IH_SRC_ID_END = 0x3f,
36 ROM_IH_SRC_ID_START = 0x40,
37 ROM_IH_SRC_ID_END = 0x5d,
[all …]
/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Dp2020ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_0_sh_mask.h7 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
8 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
9 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
10 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
11 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
12 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
13 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
14 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
16 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
17 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
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