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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dralink,rt3883-pci.txt38 address. The value must be 0. As such, 'interrupt-map' nodes do not
53 address. The value must be 0.
105 reg = <0x10140000 0x20000>;
114 #address-cells = <0>;
128 bus-range = <0 255>;
130 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
131 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
134 interrupt-map-mask = <0xf800 0 0 7>;
137 0x8800 0 0 1 &pciintc 18
138 0x8800 0 0 2 &pciintc 18
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
Dmpc8541cds.dts29 #size-cells = <0>;
31 PowerPC,8541@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8555cds.dts29 #size-cells = <0>;
31 PowerPC,8555@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8641_hpcn_36b.dts18 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
22 reg = <0x0f 0xffe05000 0x0 0x1000>;
24 ranges = <0 0 0xf 0xef800000 0x00800000
25 2 0 0xf 0xffdf8000 0x00008000
26 3 0 0xf 0xffdf0000 0x00008000>;
28 flash@0,0 {
30 reg = <0 0 0x00800000>;
35 partition@0 {
37 reg = <0x00000000 0x00300000>;
41 reg = <0x00300000 0x00100000>;
[all …]
Dmpc8560ads.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x0 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
58 ecm-law@0 {
60 reg = <0x0 0x1000>;
66 reg = <0x1000 0x1000>;
[all …]
Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
Dmpc8641_hpcn.dts16 reg = <0x00000000 0x40000000>; // 1G at 0x0
20 reg = <0xffe05000 0x1000>;
22 ranges = <0 0 0xef800000 0x00800000
23 2 0 0xffdf8000 0x00008000
24 3 0 0xffdf0000 0x00008000>;
26 flash@0,0 {
28 reg = <0 0 0x00800000>;
33 partition@0 {
35 reg = <0x00000000 0x00300000>;
39 reg = <0x00300000 0x00100000>;
[all …]
Dmpc8540ads.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8572ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00060000>;
77 reg = <0x07f60000 0x00020000>;
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dmpc834x_mds.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe2400000 0x8000>;
57 ranges = <0x0 0xe0000000 0x00100000>;
58 reg = <0xe0000000 0x00000200>;
[all …]
Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
Dmpc8379_mds.dts26 #size-cells = <0>;
28 PowerPC,8379@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x20000000>; // 512MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
55 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
Dmpc8378_mds.dts28 #size-cells = <0>;
30 PowerPC,8378@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
Dmpc832x_mds.dts39 #size-cells = <0>;
41 PowerPC,8323@0 {
43 reg = <0x0>;
48 timebase-frequency = <0>;
49 bus-frequency = <0>;
50 clock-frequency = <0>;
56 reg = <0x00000000 0x08000000>;
61 reg = <0xf8000000 0x8000>;
69 ranges = <0x0 0xe0000000 0x00100000>;
70 reg = <0xe0000000 0x00000200>;
[all …]
Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
Dmpc8377_mds.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
/Linux-v6.1/sound/soc/codecs/
Drt274.h14 #define RT274_AUDIO_FUNCTION_GROUP 0x01
15 #define RT274_DAC_OUT0 0x02
16 #define RT274_DAC_OUT1 0x03
17 #define RT274_ADC_IN2 0x08
18 #define RT274_ADC_IN1 0x09
19 #define RT274_DIG_CVT 0x0a
20 #define RT274_DMIC1 0x12
21 #define RT274_DMIC2 0x13
22 #define RT274_MIC 0x19
23 #define RT274_LINE1 0x1a
[all …]
Drt286.h14 #define RT286_AUDIO_FUNCTION_GROUP 0x01
15 #define RT286_DAC_OUT1 0x02
16 #define RT286_DAC_OUT2 0x03
17 #define RT286_ADC_IN1 0x09
18 #define RT286_ADC_IN2 0x08
19 #define RT286_MIXER_IN 0x0b
20 #define RT286_MIXER_OUT1 0x0c
21 #define RT286_MIXER_OUT2 0x0d
22 #define RT286_DMIC1 0x12
23 #define RT286_DMIC2 0x13
[all …]
Drt298.h14 #define RT298_AUDIO_FUNCTION_GROUP 0x01
15 #define RT298_DAC_OUT1 0x02
16 #define RT298_DAC_OUT2 0x03
17 #define RT298_DIG_CVT 0x06
18 #define RT298_ADC_IN1 0x09
19 #define RT298_ADC_IN2 0x08
20 #define RT298_MIXER_IN 0x0b
21 #define RT298_MIXER_OUT1 0x0c
22 #define RT298_MIXER_OUT2 0x0d
23 #define RT298_DMIC1 0x12
[all …]
/Linux-v6.1/include/linux/
Dscx200.h13 #define scx200_cb_present() (scx200_cb_base!=0)
16 #define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */
17 #define SCx200_DOCCS_CTRL 0x7c /* DOCCS Control Register */
20 #define SCx200_GPIO_SIZE 0x2c /* Size of GPIO register block */
23 #define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */
26 #define SCx200_WDT_OFFSET 0x00 /* offset within configuration block */
27 #define SCx200_WDT_SIZE 0x05 /* size */
29 #define SCx200_WDT_WDTO 0x00 /* Time-Out Register */
30 #define SCx200_WDT_WDCNFG 0x02 /* Configuration Register */
31 #define SCx200_WDT_WDSTS 0x04 /* Status Register */
[all …]
/Linux-v6.1/arch/mips/mm/
Dsc-ip22.c24 #define SC_SIZE 0x00080000
39 " li $1, 0x80 # Go 64 bit \n" in indy_sc_wipe()
43 " # Open code a dli $1, 0x9000000080000000 \n" in indy_sc_wipe()
49 " lui $1,0x9000 \n" in indy_sc_wipe()
50 " dsll $1,$1,0x10 \n" in indy_sc_wipe()
51 " ori $1,$1,0x8000 \n" in indy_sc_wipe()
52 " dsll $1,$1,0x10 \n" in indy_sc_wipe()
54 " or %0, $1 # first line to flush \n" in indy_sc_wipe()
58 "1: sw $0, 0(%0) \n" in indy_sc_wipe()
59 " bne %0, %1, 1b \n" in indy_sc_wipe()
[all …]
/Linux-v6.1/drivers/clk/qcom/
Dturingcc-qcs404.c24 .halt_reg = 0x5098,
27 .enable_reg = 0x5098,
28 .enable_mask = BIT(0),
37 .halt_reg = 0x9000,
40 .enable_reg = 0x9000,
41 .enable_mask = BIT(0),
50 .halt_reg = 0xb000,
53 .enable_reg = 0xb000,
54 .enable_mask = BIT(0),
63 .halt_reg = 0x10000,
[all …]
/Linux-v6.1/arch/arm/mach-ux500/
Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]

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