Lines Matching +full:0 +full:x9000
29 #size-cells = <0>;
31 PowerPC,8541@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
58 ecm-law@0 {
60 reg = <0x0 0x1000>;
66 reg = <0x1000 0x1000>;
73 reg = <0x2000 0x1000>;
80 reg = <0x20000 0x1000>;
82 cache-size = <0x40000>; // L2, 256K
89 #size-cells = <0>;
90 cell-index = <0>;
92 reg = <0x3000 0x100>;
102 reg = <0x21300 0x4>;
103 ranges = <0x0 0x21100 0x200>;
104 cell-index = <0>;
105 dma-channel@0 {
108 reg = <0x0 0x80>;
109 cell-index = <0>;
116 reg = <0x80 0x80>;
124 reg = <0x100 0x80>;
132 reg = <0x180 0x80>;
142 cell-index = <0>;
146 reg = <0x24000 0x1000>;
147 ranges = <0x0 0x24000 0x1000>;
156 #size-cells = <0>;
158 reg = <0x520 0x20>;
160 phy0: ethernet-phy@0 {
163 reg = <0x0>;
168 reg = <0x1>;
171 reg = <0x11>;
184 reg = <0x25000 0x1000>;
185 ranges = <0x0 0x25000 0x1000>;
194 #size-cells = <0>;
196 reg = <0x520 0x20>;
199 reg = <0x11>;
206 cell-index = <0>;
209 reg = <0x4500 0x100>; // reg base, size
210 clock-frequency = <0>; // should we fill in in uboot?
219 reg = <0x4600 0x100>; // reg base, size
220 clock-frequency = <0>; // should we fill in in uboot?
226 compatible = "fsl,sec2.0";
227 reg = <0x30000 0x10000>;
232 fsl,exec-units-mask = <0x7e>;
233 fsl,descriptor-types-mask = <0x01010ebf>;
238 #address-cells = <0>;
240 reg = <0x40000 0x40000>;
249 reg = <0x919c0 0x30>;
255 ranges = <0x0 0x80000 0x10000>;
257 data@0 {
259 reg = <0x0 0x2000 0x9000 0x1000>;
267 reg = <0x919f0 0x10 0x915f0 0x10>;
272 #address-cells = <0>;
276 reg = <0x90c00 0x80>;
283 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
286 /* IDSEL 0x10 */
287 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
288 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
289 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
290 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
292 /* IDSEL 0x11 */
293 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
294 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
295 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
296 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
298 /* IDSEL 0x12 (Slot 1) */
299 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
300 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
301 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
302 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
304 /* IDSEL 0x13 (Slot 2) */
305 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
306 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
307 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
308 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
310 /* IDSEL 0x14 (Slot 3) */
311 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
312 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
313 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
314 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
316 /* IDSEL 0x15 (Slot 4) */
317 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
318 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
319 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
320 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
323 /* IDSEL 0x12 (ISA bridge) */
324 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
325 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
326 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
327 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
330 bus-range = <0 0>;
331 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
332 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
337 reg = <0xe0008000 0x1000>;
344 reg = <0x19000 0x0 0x0 0x0 0x1>;
345 #address-cells = <0>;
354 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
357 /* IDSEL 0x15 */
358 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
359 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
360 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
361 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
364 bus-range = <0 0>;
365 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
366 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
371 reg = <0xe0009000 0x1000>;