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/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/Linux-v6.1/drivers/virt/nitro_enclaves/
Dne_misc_dev_test.c6 #define INVALID_VALUE (~0ull)
17 * Add the region from 0x1000 to (0x1000 + 0x200000 - 1):
22 * num = 0
25 {0x1000, 0x200000, -EINVAL, 0, INVALID_VALUE, INVALID_VALUE},
28 * Add the region from 0x200000 to (0x200000 + 0x1000 - 1):
33 * num = 0
36 {0x200000, 0x1000, -EINVAL, 0, INVALID_VALUE, INVALID_VALUE},
39 * Add the region from 0x200000 to (0x200000 + 0x200000 - 1):
46 * {start=0x200000, end=0x3fffff}, // len=0x200000
49 {0x200000, 0x200000, 0, 1, 0x200000, 0x200000},
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Darmada-398-db.dts23 reg = <0x00000000 0x80000000>; /* 2 GB */
27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
32 pinctrl-0 = <&i2c0_pins>;
39 pinctrl-0 = <&uart0_pins>;
45 pinctrl-0 = <&uart1_pins>;
62 pcie@1,0 {
66 pcie@2,0 {
70 pcie@3,0 {
79 pinctrl-0 = <&spi1_pins>;
[all …]
Darmada-390-db.dts24 reg = <0x00000000 0x80000000>; /* 2 GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
38 reg = <0x50>;
62 pcie@1,0 {
67 pcie@2,0 {
72 pcie@3,0 {
81 pinctrl-0 = <&spi1_pins>;
89 reg = <0>; /* Chip select 0 */
97 partition@0 {
[all …]
Darmada-375-db.dts24 memory@0 {
26 reg = <0x00000000 0x40000000>; /* 1 GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
57 pinctrl-0 = <&spi0_pins>;
67 flash@0 {
[all …]
Darmada-388-db.dts25 reg = <0x00000000 0x10000000>; /* 256 MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
40 #sound-dai-cells = <0>;
42 reg = <0x4a>;
73 bm,pool-long = <0>;
78 phy0: ethernet-phy@0 {
[all …]
Dnuvoton-npcm750-evb.dts50 reg = <0x0 0x20000000>;
70 flash@0 {
75 reg = <0>;
81 bbuboot1@0 {
83 reg = <0x0000000 0x80000>;
88 reg = <0x0080000 0x80000>;
93 reg = <0x0100000 0x40000>;
98 reg = <0x0140000 0xC0000>;
102 reg = <0x0200000 0x400000>;
106 reg = <0x0600000 0x700000>;
[all …]
Darmada-370-rd.dts11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0x00000000 0x20000000>; /* 512 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
59 pinctrl-0 = <&ge1_rgmii_pins>;
70 pinctrl-0 = <&sdio_pins1>;
[all …]
Darmada-370-db.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
33 memory@0 {
35 reg = <0x00000000 0x40000000>; /* 1 GB */
39 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
40 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
41 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
53 pinctrl-0 = <&ge0_rgmii_pins>;
60 pinctrl-0 = <&ge1_rgmii_pins>;
[all …]
Darmada-xp-db.dts14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
43 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
44 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
[all …]
Dat91sam9x5cm.dtsi11 reg = <0x20000000 0x8000000>;
27 timer@0 {
29 reg = <0>;
40 pinctrl_1wire_cm: 1wire_cm-0 {
52 pinctrl-0 = <&pinctrl_ebi_addr_nand
59 pinctrl-0 = <&pinctrl_nand_oe_we
65 reg = <0x3 0x0 0x800000>;
80 at91bootstrap@0 {
82 reg = <0x0 0x40000>;
87 reg = <0x40000 0xc0000>;
[all …]
Dat91-cosino.dtsi24 reg = <0x20000000 0x8000000>;
49 pinctrl-0 = <&pinctrl_ebi_addr_nand
55 pinctrl-0 = <&pinctrl_nand_oe_we
62 reg = <0x3 0x0 0x800000>;
77 at91bootstrap@0 {
79 reg = <0x0 0x40000>;
84 reg = <0x40000 0x80000>;
89 reg = <0xc0000 0x140000>;
94 reg = <0x200000 0x600000>;
99 reg = <0x800000 0x0f800000>;
[all …]
/Linux-v6.1/arch/powerpc/kernel/
Dvecemu.c25 0x800000,
26 0x8b95c2,
27 0x9837f0,
28 0xa5fed7,
29 0xb504f3,
30 0xc5672a,
31 0xd744fd,
32 0xeac0c7
45 exp = ((s >> 23) & 0xff) - 127; in eexp2()
48 if (exp == 128 && (s & 0x7fffff) != 0) in eexp2()
[all …]
/Linux-v6.1/drivers/net/wireless/intel/iwlwifi/
Diwl-agn-hw.h12 #define IWLAGN_RTC_INST_LOWER_BOUND (0x000000)
13 #define IWLAGN_RTC_INST_UPPER_BOUND (0x020000)
15 #define IWLAGN_RTC_DATA_LOWER_BOUND (0x800000)
16 #define IWLAGN_RTC_DATA_UPPER_BOUND (0x80C000)
23 #define IWL60_RTC_INST_LOWER_BOUND (0x000000)
24 #define IWL60_RTC_INST_UPPER_BOUND (0x040000)
25 #define IWL60_RTC_DATA_LOWER_BOUND (0x800000)
26 #define IWL60_RTC_DATA_UPPER_BOUND (0x814000)
42 #define IWLAGN_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm: 1 milliwatt */
50 #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */
/Linux-v6.1/arch/arm64/boot/dts/marvell/
Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Ds5p-mfc.txt44 reg = <0x13400000 0x10000>;
45 interrupts = <0 94 0>;
62 reg = <0x51000000 0x800000>;
68 reg = <0x43000000 0x800000>;
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dmpc8548cds_32b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
23 0x1 0x0 0x0 0xf8004000 0x00001000>;
28 ranges = <0 0x0 0xe0000000 0x100000>;
32 reg = <0 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 reg = <0 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
[all …]
Dmpc8548cds_36b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0xf 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
23 0x1 0x0 0xf 0xf8004000 0x00001000>;
28 ranges = <0 0xf 0xe0000000 0x100000>;
32 reg = <0xf 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 reg = <0xf 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
[all …]
/Linux-v6.1/arch/mips/boot/dts/lantiq/
Ddanube.dtsi8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
45 reg = <0x101000 0x1000>;
50 reg = <0x102000 0x1000>;
55 reg = <0x103000 0x1000>;
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dpq2fads.dts26 #size-cells = <0>;
28 cpu@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x60>;
52 ranges = <0x0 0x0 0xff800000 0x800000
53 0x1 0x0 0xf4500000 0x8000
54 0x8 0x0 0xf8200000 0x8000>;
[all …]

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