Searched +full:0 +full:x80000 (Results 1 – 25 of 638) sorted by relevance
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/Linux-v6.1/drivers/misc/habanalabs/include/gaudi/asic_reg/ |
D | tpc0_cfg_masks.h | 23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF 35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 [all …]
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/Linux-v6.1/arch/arm/boot/dts/ |
D | imx28-apf28.dts | 15 reg = <0x40000000 0x08000000>; 22 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; 25 partition@0 { 27 reg = <0x0 0x300000>; 32 reg = <0x300000 0x80000>; 37 reg = <0x380000 0x80000>; 42 reg = <0x400000 0x80000>; 47 reg = <0x480000 0x80000>; 52 reg = <0x500000 0x800000>; 57 reg = <0xd00000 0xf300000>; [all …]
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D | imx27-apf27.dts | 18 reg = <0xa0000000 0x04000000>; 23 clock-frequency = <0>; 30 MX27_PAD_SD3_CMD__FEC_TXD0 0x0 31 MX27_PAD_SD3_CLK__FEC_TXD1 0x0 32 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 33 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 34 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 35 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 36 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 37 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 [all …]
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D | omap3430-sdp.dts | 15 reg = <0x80000000 0x10000000>; /* 256 MB */ 23 reg = <0x48>; 50 ranges = <0 0 0x10000000 0x08000000>, 51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ 52 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ 54 nor@0,0 { 59 reg = <0 0 0x08000000>; 63 gpmc,cs-on-ns = <0>; 84 partition@0 { 86 reg = <0 0x40000>; [all …]
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D | bcm958625-meraki-mx6x-common.dtsi | 55 reg = <0x50>; 62 reg = <0x66 0x6>; 68 nand@0 { 70 reg = <0>; 81 partition@0 { 83 reg = <0x0 0x80000>; 89 reg = <0x80000 0x80000>; 95 reg = <0x100000 0x300000>; 100 reg = <0x400000 0x100000>; 105 reg = <0x500000 0x300000>; [all …]
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D | aspeed-bmc-ibm-everest.dts | 157 reg = <0x80000000 0x40000000>; 168 reg = <0xb8000000 0x04000000>; /* 64M */ 174 reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ 175 record-size = <0x8000>; 176 console-size = <0x8000>; 177 ftrace-size = <0x8000>; 178 pmsg-size = <0x8000>; 186 reg = <0xbf000000 0x01000000>; /* 16M */ 224 gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; 258 pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default [all …]
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D | am57-pruss.dtsi | 11 reg = <0x4b226000 0x4>, 12 <0x4b226004 0x4>; 23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>; 27 ranges = <0x00000000 0x4b200000 0x80000>; 29 pruss1: pruss@0 { 31 reg = <0x0 0x80000>; 36 pruss1_mem: memories@0 { 37 reg = <0x0 0x2000>, 38 <0x2000 0x2000>, 39 <0x10000 0x8000>; [all …]
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D | keystone-k2l-evm.dts | 23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 33 #clock-cells = <0>; 56 reg = <0x50>; 67 ti,cs-chipselect = <0>; 77 nand@0,0 { 81 reg = <0 0 0x4000000 82 1 0 0x0000100>; 84 ti,davinci-chipselect = <0>; 85 ti,davinci-mask-ale = <0x2000>; 86 ti,davinci-mask-cle = <0x4000>; [all …]
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D | keystone-k2e-evm.dts | 23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 34 #clock-cells = <0>; 41 #clock-cells = <0>; 48 #clock-cells = <0>; 83 reg = <0x50>; 94 ti,cs-chipselect = <0>; 104 nand@0,0 { 108 reg = <0 0 0x4000000 109 1 0 0x0000100>; 111 ti,davinci-chipselect = <0>; [all …]
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D | orion5x-lacie-ethernet-disk-mini-v2.dts | 24 reg = <0x00000000 0x4000000>; /* 64 MB */ 33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, 34 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, 35 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>; 40 pinctrl-0 = <&pmx_power_button>; 43 #size-cells = <0>; 53 pinctrl-0 = <&pmx_power_led>; 69 devbus,badr-skew-ps = <0>; 88 flash@0 { 90 reg = <0 0x80000>; [all …]
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D | armada-380.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 46 bus-range = <0x00 0xff>; 49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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D | kirkwood-6282.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 23 pcie0: pcie@1,0 { 25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; [all …]
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D | spear320-hmi.dts | 18 reg = <0 0x40000000>; 25 pinctrl-0 = <&state_default>; 102 partition@0 { 104 reg = <0x0 0x80000>; 108 reg = <0x80000 0x140000>; 112 reg = <0x1C0000 0x40000>; 116 reg = <0x200000 0x40000>; 120 reg = <0x240000 0xC00000>; 124 reg = <0xE40000 0x0>; 131 #size-cells = <0>; [all …]
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D | keystone-k2hk-evm.dts | 23 reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 56 #clock-cells = <0>; 63 #clock-cells = <0>; 70 #clock-cells = <0>; 77 #clock-cells = <0>; 84 #clock-cells = <0>; 111 ti,cs-chipselect = <0>; 121 nand@0,0 { 125 reg = <0 0 0x4000000 126 1 0 0x0000100>; [all …]
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D | orion5x-lacie-d2-network.dts | 20 reg = <0x00000000 0x4000000>; /* 64 MB */ 29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, 30 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, 31 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>; 36 pinctrl-0 = <&pmx_buttons>; 39 #size-cells = <0>; 64 #size-cells = <0>; 65 pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; 68 sata0_power: regulator@0 { 70 reg = <0>; [all …]
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/Linux-v6.1/arch/mips/include/asm/ip32/ |
D | mace.h | 18 #define MACE_BASE 0x1f000000 /* physical */ 43 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0 44 #define MACEPCI_ERROR_DEVSEL_FAST 0 45 #define MACEPCI_ERROR_DEVSEL_MED 0x40 46 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80 48 #define MACEPCI_ERROR_66MHZ BIT(0) 51 #define MACEPCI_CONTROL_INT_MASK 0xff 61 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000 71 unsigned int _pad[0xcf8/4 - 4]; 79 #define MACEPCI_LOW_MEMORY 0x1a000000 [all …]
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/Linux-v6.1/arch/arm64/boot/dts/amd/ |
D | amd-seattle-xgbe-b.dtsi | 10 #clock-cells = <0>; 17 #clock-cells = <0>; 24 #clock-cells = <0>; 31 #clock-cells = <0>; 38 reg = <0 0xe0700000 0 0x80000>, 39 <0 0xe0780000 0 0x80000>, 40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ 41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ 42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ 43 interrupts = <0 325 4>, [all …]
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/Linux-v6.1/arch/arm64/boot/dts/xilinx/ |
D | zynqmp-sm-k26-revA.dts | 47 memory@0 { 49 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 81 &qspi { /* MIO 0-5 - U143 */ 83 flash@0 { /* MT25QU512A */ 87 reg = <0>; 91 partition@0 { 93 reg = <0x0 0x80000>; /* 512KB */ 99 reg = <0x80000 0x80000>; /* 512KB */ 105 reg = <0x100000 0x20000>; /* 128KB */ 109 reg = <0x120000 0x20000>; /* 128KB */ [all …]
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/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt76x2/ |
D | mcu.h | 12 #define MT_MCU_CPU_CTL 0x0704 13 #define MT_MCU_CLOCK_CTL 0x0708 14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740 15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744 16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748 18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000 19 #define MT_MCU_ROM_PATCH_ADDR 0x90000 21 #define MT_MCU_ILM_OFFSET 0x80000 23 #define MT_MCU_DLM_OFFSET 0x100000 24 #define MT_MCU_DLM_ADDR 0x90000 [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/remoteproc/ |
D | ti,pru-rproc.yaml | 19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary 21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two 46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs 79 pattern: "^rtu@[0-9a-f]+$" 91 pattern: "^txpru@[0-9a-f]+" 95 pattern: "^pru@[0-9a-f]+$" 108 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 112 ranges = <0x0 0x300000 0x80000>; 114 pruss: pruss@0 { 116 reg = <0x0 0x80000>; [all …]
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/Linux-v6.1/drivers/net/ethernet/netronome/nfp/nfpcore/ |
D | nfp_dev.c | 13 .qc_idx_mask = GENMASK(8, 0), 14 .qc_addr_offset = 0x400000, 19 .pcie_cfg_expbar_offset = 0x0a00, 20 .pcie_expl_offset = 0xd000, 21 .qc_area_sz = 0x100000, 25 .qc_idx_mask = GENMASK(8, 0), 26 .qc_addr_offset = 0, 32 .qc_idx_mask = GENMASK(7, 0), 33 .qc_addr_offset = 0x80000, 38 .pcie_cfg_expbar_offset = 0x0400, [all …]
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/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_5_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 [all …]
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/Linux-v6.1/drivers/clk/imx/ |
D | clk-imx8qxp-lpcg.h | 11 #define LSIO_PWM_0_LPCG 0x00000 12 #define LSIO_PWM_1_LPCG 0x10000 13 #define LSIO_PWM_2_LPCG 0x20000 14 #define LSIO_PWM_3_LPCG 0x30000 15 #define LSIO_PWM_4_LPCG 0x40000 16 #define LSIO_PWM_5_LPCG 0x50000 17 #define LSIO_PWM_6_LPCG 0x60000 18 #define LSIO_PWM_7_LPCG 0x70000 19 #define LSIO_GPIO_0_LPCG 0x80000 20 #define LSIO_GPIO_1_LPCG 0x90000 [all …]
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/Linux-v6.1/arch/powerpc/boot/dts/fsl/ |
D | c293si-post.dtsi | 39 interrupts = <19 2 0 0>; 42 /* controller at 0xa000 */ 48 bus-range = <0 255>; 50 interrupts = <16 2 0 0>; 52 pcie@0 { 53 reg = <0 0 0 0 0>; 58 interrupts = <16 2 0 0>; 59 interrupt-map-mask = <0xf800 0 0 7>; 61 /* IDSEL 0x0 */ 62 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 [all …]
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/Linux-v6.1/drivers/gpu/drm/i915/display/ |
D | intel_dmc_regs.h | 12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 14 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 15 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 20 0x400 * ((dmc_id) - 1)) 22 #define __DMC_REG_MMIO_BASE 0x8f000 33 #define _DMC_EVT_HTP_0 0x8f004 38 #define _DMC_EVT_CTL_0 0x8f034 46 #define DMC_EVT_CTL_TYPE_LEVEL_0 0 52 #define DMC_EVT_CTL_EVENT_ID_FALSE 0x01 54 #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf [all …]
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