Home
last modified time | relevance | path

Searched +full:0 +full:x4e000 (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dqcom,q6sstopcc.yaml40 reg = <0x07500000 0x4e000>, <0x07550000 0x10000>;
/Linux-v5.15/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.txt75 reg = <0x0 0x30000000 0x0 0x50000>;
78 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
82 reg = <0x0 0x4e000 0x0 0x1000>;
89 reg = <0x0 0x4f000 0x0 0x1000>;
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi14 bus@0 {
19 ranges = <0x0 0x0 0x0 0x40000000>;
23 reg = <0x00100000 0xf000>,
24 <0x0010f000 0x1000>;
30 reg = <0x03100000 0x10000>;
41 reg = <0x03460000 0x20000>;
53 reg = <0x03810000 0x10000>;
60 reg = <0x03c00000 0xa0000>;
78 reg = <0x0c150000 0x90000>;
84 * Shared interrupt 0 is routed only to AON/SPE, so
[all …]
Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
85 ranges = <0x02900000 0x0 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135 reg = <0x02a41000 0x1000>,
[all …]
Dtegra194.dtsi19 bus@0 {
23 ranges = <0x0 0x0 0x0 0x40000000>;
27 reg = <0x00100000 0xf000>,
28 <0x0010f000 0x1000>;
34 reg = <0x2200000 0x10000>,
35 <0x2210000 0x10000>;
52 reg = <0x02490000 0x10000>;
70 snps,burst-map = <0x7>;
84 ranges = <0x02900000 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
[all …]
/Linux-v5.15/drivers/clk/qcom/
Dgcc-sm6115.c49 { 500000000, 1250000000, 0 },
57 .offset = 0x0,
62 .enable_reg = 0x79000,
63 .enable_mask = BIT(0),
76 { 0x1, 2 },
81 .offset = 0x0,
97 [PLL_OFF_L_VAL] = 0x04,
98 [PLL_OFF_ALPHA_VAL] = 0x08,
99 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
100 [PLL_OFF_TEST_CTL] = 0x10,
[all …]
Dgcc-sm6125.c43 .offset = 0x0,
46 .enable_reg = 0x79000,
47 .enable_mask = BIT(0),
86 .offset = 0x3000,
89 .enable_reg = 0x79000,
103 .offset = 0x4000,
106 .enable_reg = 0x79000,
120 .offset = 0x5000,
123 .enable_reg = 0x79000,
137 .offset = 0x6000,
[all …]
Dgcc-qcs404.c42 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
84 { P_XO, 0 },
98 { P_XO, 0 },
110 { P_XO, 0 },
124 { P_XO, 0 },
138 { P_XO, 0 },
156 { P_XO, 0 },
168 { P_XO, 0 },
[all …]
Dgcc-msm8998.c39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
[all …]
Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
Dgcc-msm8996.c50 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
106 { P_XO, 0 },
120 { P_XO, 0 },
134 { P_XO, 0 },
152 { P_XO, 0 },
183 .offset = 0x00000,
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
Dgcc-msm8953.c41 .offset = 0x21000,
44 .enable_reg = 0x45000,
45 .enable_mask = BIT(0),
71 .offset = 0x21000,
84 .offset = 0x4a000,
87 .enable_reg = 0x45000,
101 .offset = 0x4a000,
114 { 1000000000, 2000000000, 0 },
119 .config_ctl_val = 0x4001055b,
120 .early_output_mask = 0,
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]