Lines Matching +full:0 +full:x4e000
49 { 500000000, 1250000000, 0 },
57 .offset = 0x0,
62 .enable_reg = 0x79000,
63 .enable_mask = BIT(0),
76 { 0x1, 2 },
81 .offset = 0x0,
97 [PLL_OFF_L_VAL] = 0x04,
98 [PLL_OFF_ALPHA_VAL] = 0x08,
99 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
100 [PLL_OFF_TEST_CTL] = 0x10,
101 [PLL_OFF_TEST_CTL_U] = 0x14,
102 [PLL_OFF_USER_CTL] = 0x18,
103 [PLL_OFF_CONFIG_CTL] = 0x1C,
104 [PLL_OFF_STATUS] = 0x20,
108 { 0x0, 1 },
113 .offset = 0x0,
129 .l = 0x3c,
130 .vco_val = 0x1 << 20,
132 .main_output_mask = BIT(0),
133 .config_ctl_val = 0x4001055b,
137 .offset = 0xa000,
142 .enable_reg = 0x79000,
156 { 0x0, 1 },
161 .offset = 0xa000,
178 .l = 0x1F,
179 .alpha = 0x0,
180 .alpha_hi = 0x40,
182 .vco_val = 0x2 << 20,
184 .config_ctl_val = 0x4001055b,
188 .offset = 0xb000,
194 .enable_reg = 0x79000,
208 { 0x0, 1 },
213 .offset = 0xb000,
229 .offset = 0x3000,
234 .enable_reg = 0x79000,
248 .offset = 0x4000,
253 .enable_reg = 0x79000,
267 { 0x0, 1 },
272 .offset = 0x4000,
287 .offset = 0x6000,
292 .enable_reg = 0x79000,
306 { 0x1, 2 },
311 .offset = 0x6000,
326 .offset = 0x7000,
331 .enable_reg = 0x79000,
345 { 0x0, 1 },
350 .offset = 0x7000,
366 .l = 0x29,
367 .alpha = 0xAAAAAAAA,
368 .alpha_hi = 0xAA,
370 .vco_val = 0x2 << 20,
372 .main_output_mask = BIT(0),
374 .post_div_val = 0x1 << 8,
376 .config_ctl_val = 0x4001055b,
380 .offset = 0x8000,
386 .enable_reg = 0x79000,
400 { 0x1, 2 },
405 .offset = 0x8000,
422 .l = 0x3C,
423 .alpha = 0x0,
424 .post_div_val = 0x1 << 8,
426 .main_output_mask = BIT(0),
427 .config_ctl_val = 0x00004289,
431 .offset = 0x9000,
436 .enable_reg = 0x79000,
450 { 0x1, 2 },
455 .offset = 0x9000,
471 { P_BI_TCXO, 0 },
483 { P_BI_TCXO, 0 },
497 { P_BI_TCXO, 0 },
511 { P_BI_TCXO, 0 },
527 { P_BI_TCXO, 0 },
541 { P_BI_TCXO, 0 },
559 { P_BI_TCXO, 0 },
579 { P_BI_TCXO, 0 },
597 { P_BI_TCXO, 0 },
617 { P_BI_TCXO, 0 },
637 { P_BI_TCXO, 0 },
655 { P_BI_TCXO, 0 },
671 { P_BI_TCXO, 0 },
681 { P_BI_TCXO, 0 },
691 F(19200000, P_BI_TCXO, 1, 0, 0),
692 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
693 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
694 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
699 .cmd_rcgr = 0x5802c,
700 .mnd_width = 0,
714 F(19200000, P_BI_TCXO, 1, 0, 0),
715 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
720 .cmd_rcgr = 0x56000,
721 .mnd_width = 0,
735 F(19200000, P_BI_TCXO, 1, 0, 0),
736 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
737 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
738 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
743 .cmd_rcgr = 0x59000,
744 .mnd_width = 0,
758 .cmd_rcgr = 0x5901c,
759 .mnd_width = 0,
773 .cmd_rcgr = 0x59038,
774 .mnd_width = 0,
788 F(19200000, P_BI_TCXO, 1, 0, 0),
795 .cmd_rcgr = 0x51000,
810 .cmd_rcgr = 0x5101c,
825 .cmd_rcgr = 0x51038,
840 .cmd_rcgr = 0x51054,
855 F(19200000, P_BI_TCXO, 1, 0, 0),
856 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
857 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
862 .cmd_rcgr = 0x55024,
863 .mnd_width = 0,
877 F(19200000, P_BI_TCXO, 1, 0, 0),
878 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
879 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
880 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
881 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
886 .cmd_rcgr = 0x55004,
887 .mnd_width = 0,
901 F(19200000, P_BI_TCXO, 1, 0, 0),
902 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
903 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
904 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
905 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
906 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
907 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
908 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
909 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
910 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
911 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
912 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
913 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
914 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
915 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
916 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
921 .cmd_rcgr = 0x52004,
936 F(19200000, P_BI_TCXO, 1, 0, 0),
937 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
938 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
939 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
940 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
941 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
946 .cmd_rcgr = 0x52094,
947 .mnd_width = 0,
961 .cmd_rcgr = 0x52024,
976 .cmd_rcgr = 0x520b4,
977 .mnd_width = 0,
991 .cmd_rcgr = 0x52044,
1006 .cmd_rcgr = 0x520d4,
1007 .mnd_width = 0,
1021 F(19200000, P_BI_TCXO, 1, 0, 0),
1022 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1024 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
1029 .cmd_rcgr = 0x52064,
1044 F(19200000, P_BI_TCXO, 1, 0, 0),
1045 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1046 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
1051 .cmd_rcgr = 0x58010,
1052 .mnd_width = 0,
1066 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1067 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1068 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1069 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
1074 .cmd_rcgr = 0x4d004,
1088 .cmd_rcgr = 0x4e004,
1102 .cmd_rcgr = 0x4f004,
1116 F(19200000, P_BI_TCXO, 1, 0, 0),
1117 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1122 .cmd_rcgr = 0x20010,
1123 .mnd_width = 0,
1138 F(19200000, P_BI_TCXO, 1, 0, 0),
1143 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1146 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1150 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1151 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1163 .cmd_rcgr = 0x1f148,
1179 .cmd_rcgr = 0x1f278,
1195 .cmd_rcgr = 0x1f3a8,
1211 .cmd_rcgr = 0x1f4d8,
1227 .cmd_rcgr = 0x1f608,
1243 .cmd_rcgr = 0x1f738,
1256 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1257 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1258 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1259 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1264 .cmd_rcgr = 0x38028,
1278 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1279 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1280 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1281 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1282 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1287 .cmd_rcgr = 0x38010,
1288 .mnd_width = 0,
1302 F(19200000, P_BI_TCXO, 1, 0, 0),
1303 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1304 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1305 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1306 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1311 .cmd_rcgr = 0x1e00c,
1326 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1327 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1328 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1329 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1330 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1335 .cmd_rcgr = 0x45020,
1349 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1350 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1351 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1352 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1357 .cmd_rcgr = 0x45048,
1358 .mnd_width = 0,
1371 F(9600000, P_BI_TCXO, 2, 0, 0),
1372 F(19200000, P_BI_TCXO, 1, 0, 0),
1377 .cmd_rcgr = 0x4507c,
1378 .mnd_width = 0,
1391 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1392 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1393 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1398 .cmd_rcgr = 0x45060,
1399 .mnd_width = 0,
1412 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1413 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1414 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1415 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1420 .cmd_rcgr = 0x1a01c,
1434 F(19200000, P_BI_TCXO, 1, 0, 0),
1439 .cmd_rcgr = 0x1a034,
1440 .mnd_width = 0,
1453 .reg = 0x1a04c,
1454 .shift = 0,
1466 .cmd_rcgr = 0x1a060,
1467 .mnd_width = 0,
1480 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1481 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1482 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1483 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1488 .cmd_rcgr = 0x58060,
1489 .mnd_width = 0,
1503 .halt_reg = 0x1d004,
1505 .hwcg_reg = 0x1d004,
1508 .enable_reg = 0x1d004,
1509 .enable_mask = BIT(0),
1518 .halt_reg = 0x1d008,
1520 .hwcg_reg = 0x1d008,
1523 .enable_reg = 0x1d008,
1524 .enable_mask = BIT(0),
1533 .halt_reg = 0x71154,
1535 .hwcg_reg = 0x71154,
1538 .enable_reg = 0x71154,
1539 .enable_mask = BIT(0),
1548 .halt_reg = 0x23004,
1550 .hwcg_reg = 0x23004,
1553 .enable_reg = 0x79004,
1563 .halt_reg = 0x17070,
1565 .hwcg_reg = 0x17070,
1568 .enable_reg = 0x79004,
1578 .halt_reg = 0x1706c,
1580 .hwcg_reg = 0x1706c,
1583 .enable_reg = 0x79004,
1593 .halt_reg = 0x17008,
1595 .hwcg_reg = 0x17008,
1598 .enable_reg = 0x17008,
1599 .enable_mask = BIT(0),
1609 .halt_reg = 0x17028,
1612 .enable_reg = 0x17028,
1613 .enable_mask = BIT(0),
1623 .halt_reg = 0x58044,
1626 .enable_reg = 0x58044,
1627 .enable_mask = BIT(0),
1641 .halt_reg = 0x5804c,
1643 .hwcg_reg = 0x5804c,
1646 .enable_reg = 0x5804c,
1647 .enable_mask = BIT(0),
1656 .halt_reg = 0x58050,
1658 .hwcg_reg = 0x58050,
1661 .enable_reg = 0x58050,
1662 .enable_mask = BIT(0),
1671 .halt_reg = 0x56018,
1674 .enable_reg = 0x56018,
1675 .enable_mask = BIT(0),
1689 .halt_reg = 0x52088,
1692 .enable_reg = 0x52088,
1693 .enable_mask = BIT(0),
1707 .halt_reg = 0x5208c,
1710 .enable_reg = 0x5208c,
1711 .enable_mask = BIT(0),
1725 .halt_reg = 0x52090,
1728 .enable_reg = 0x52090,
1729 .enable_mask = BIT(0),
1743 .halt_reg = 0x59018,
1746 .enable_reg = 0x59018,
1747 .enable_mask = BIT(0),
1761 .halt_reg = 0x59034,
1764 .enable_reg = 0x59034,
1765 .enable_mask = BIT(0),
1779 .halt_reg = 0x59050,
1782 .enable_reg = 0x59050,
1783 .enable_mask = BIT(0),
1797 .halt_reg = 0x51018,
1800 .enable_reg = 0x51018,
1801 .enable_mask = BIT(0),
1815 .halt_reg = 0x51034,
1818 .enable_reg = 0x51034,
1819 .enable_mask = BIT(0),
1833 .halt_reg = 0x51050,
1836 .enable_reg = 0x51050,
1837 .enable_mask = BIT(0),
1851 .halt_reg = 0x5106c,
1854 .enable_reg = 0x5106c,
1855 .enable_mask = BIT(0),
1869 .halt_reg = 0x58054,
1872 .enable_reg = 0x58054,
1873 .enable_mask = BIT(0),
1882 .halt_reg = 0x5503c,
1885 .enable_reg = 0x5503c,
1886 .enable_mask = BIT(0),
1900 .halt_reg = 0x5501c,
1903 .enable_reg = 0x5501c,
1904 .enable_mask = BIT(0),
1918 .halt_reg = 0x5805c,
1921 .enable_reg = 0x5805c,
1922 .enable_mask = BIT(0),
1931 .halt_reg = 0x5201c,
1934 .enable_reg = 0x5201c,
1935 .enable_mask = BIT(0),
1949 .halt_reg = 0x5207c,
1952 .enable_reg = 0x5207c,
1953 .enable_mask = BIT(0),
1967 .halt_reg = 0x520ac,
1970 .enable_reg = 0x520ac,
1971 .enable_mask = BIT(0),
1985 .halt_reg = 0x5203c,
1988 .enable_reg = 0x5203c,
1989 .enable_mask = BIT(0),
2003 .halt_reg = 0x52080,
2006 .enable_reg = 0x52080,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x520cc,
2024 .enable_reg = 0x520cc,
2025 .enable_mask = BIT(0),
2039 .halt_reg = 0x5205c,
2042 .enable_reg = 0x5205c,
2043 .enable_mask = BIT(0),
2057 .halt_reg = 0x52084,
2060 .enable_reg = 0x52084,
2061 .enable_mask = BIT(0),
2075 .halt_reg = 0x520ec,
2078 .enable_reg = 0x520ec,
2079 .enable_mask = BIT(0),
2093 .halt_reg = 0x58028,
2096 .enable_reg = 0x58028,
2097 .enable_mask = BIT(0),
2111 .halt_reg = 0x1a084,
2113 .hwcg_reg = 0x1a084,
2116 .enable_reg = 0x1a084,
2117 .enable_mask = BIT(0),
2131 .halt_reg = 0x2b004,
2133 .hwcg_reg = 0x2b004,
2136 .enable_reg = 0x79004,
2147 .halt_reg = 0x1700c,
2149 .hwcg_reg = 0x1700c,
2152 .enable_reg = 0x1700c,
2153 .enable_mask = BIT(0),
2163 .reg = 0x17058,
2164 .shift = 0,
2177 .enable_reg = 0x79004,
2192 .halt_reg = 0x17020,
2194 .hwcg_reg = 0x17020,
2197 .enable_reg = 0x17020,
2198 .enable_mask = BIT(0),
2207 .halt_reg = 0x17064,
2209 .hwcg_reg = 0x17064,
2212 .enable_reg = 0x7900c,
2222 .halt_reg = 0x1702c,
2225 .enable_reg = 0x1702c,
2226 .enable_mask = BIT(0),
2236 .halt_reg = 0x4d000,
2239 .enable_reg = 0x4d000,
2240 .enable_mask = BIT(0),
2254 .halt_reg = 0x4e000,
2257 .enable_reg = 0x4e000,
2258 .enable_mask = BIT(0),
2272 .halt_reg = 0x4f000,
2275 .enable_reg = 0x4f000,
2276 .enable_mask = BIT(0),
2290 .halt_reg = 0x36004,
2292 .hwcg_reg = 0x36004,
2295 .enable_reg = 0x36004,
2296 .enable_mask = BIT(0),
2308 .enable_reg = 0x79004,
2325 .enable_reg = 0x79004,
2340 .halt_reg = 0x36100,
2343 .enable_reg = 0x36100,
2344 .enable_mask = BIT(0),
2353 .halt_reg = 0x3600c,
2355 .hwcg_reg = 0x3600c,
2358 .enable_reg = 0x3600c,
2359 .enable_mask = BIT(0),
2368 .halt_reg = 0x36018,
2371 .enable_reg = 0x36018,
2372 .enable_mask = BIT(0),
2381 .halt_reg = 0x36048,
2383 .hwcg_reg = 0x36048,
2386 .enable_reg = 0x79004,
2396 .halt_reg = 0x2000c,
2399 .enable_reg = 0x2000c,
2400 .enable_mask = BIT(0),
2414 .halt_reg = 0x20004,
2416 .hwcg_reg = 0x20004,
2419 .enable_reg = 0x20004,
2420 .enable_mask = BIT(0),
2429 .halt_reg = 0x20008,
2432 .enable_reg = 0x20008,
2433 .enable_mask = BIT(0),
2442 .halt_reg = 0x21004,
2444 .hwcg_reg = 0x21004,
2447 .enable_reg = 0x79004,
2457 .halt_reg = 0x17014,
2459 .hwcg_reg = 0x17014,
2462 .enable_reg = 0x7900c,
2463 .enable_mask = BIT(0),
2472 .halt_reg = 0x17060,
2474 .hwcg_reg = 0x17060,
2477 .enable_reg = 0x7900c,
2487 .halt_reg = 0x17018,
2489 .hwcg_reg = 0x17018,
2492 .enable_reg = 0x7900c,
2502 .halt_reg = 0x36040,
2504 .hwcg_reg = 0x36040,
2507 .enable_reg = 0x7900c,
2517 .halt_reg = 0x17010,
2519 .hwcg_reg = 0x17010,
2522 .enable_reg = 0x79004,
2532 .halt_reg = 0x1f014,
2535 .enable_reg = 0x7900c,
2545 .halt_reg = 0x1f00c,
2548 .enable_reg = 0x7900c,
2558 .halt_reg = 0x1f144,
2561 .enable_reg = 0x7900c,
2576 .halt_reg = 0x1f274,
2579 .enable_reg = 0x7900c,
2594 .halt_reg = 0x1f3a4,
2597 .enable_reg = 0x7900c,
2612 .halt_reg = 0x1f4d4,
2615 .enable_reg = 0x7900c,
2630 .halt_reg = 0x1f604,
2633 .enable_reg = 0x7900c,
2648 .halt_reg = 0x1f734,
2651 .enable_reg = 0x7900c,
2666 .halt_reg = 0x1f004,
2668 .hwcg_reg = 0x1f004,
2671 .enable_reg = 0x7900c,
2681 .halt_reg = 0x1f008,
2683 .hwcg_reg = 0x1f008,
2686 .enable_reg = 0x7900c,
2696 .halt_reg = 0x38008,
2699 .enable_reg = 0x38008,
2700 .enable_mask = BIT(0),
2709 .halt_reg = 0x38004,
2712 .enable_reg = 0x38004,
2713 .enable_mask = BIT(0),
2727 .halt_reg = 0x3800c,
2729 .hwcg_reg = 0x3800c,
2732 .enable_reg = 0x3800c,
2733 .enable_mask = BIT(0),
2747 .halt_reg = 0x1e008,
2750 .enable_reg = 0x1e008,
2751 .enable_mask = BIT(0),
2760 .halt_reg = 0x1e004,
2763 .enable_reg = 0x1e004,
2764 .enable_mask = BIT(0),
2778 .halt_reg = 0x2b06c,
2780 .hwcg_reg = 0x2b06c,
2783 .enable_reg = 0x79004,
2784 .enable_mask = BIT(0),
2794 .halt_reg = 0x45098,
2797 .enable_reg = 0x45098,
2798 .enable_mask = BIT(0),
2812 .halt_reg = 0x1a080,
2814 .hwcg_reg = 0x1a080,
2817 .enable_reg = 0x1a080,
2818 .enable_mask = BIT(0),
2832 .halt_reg = 0x8c000,
2835 .enable_reg = 0x8c000,
2836 .enable_mask = BIT(0),
2845 .halt_reg = 0x45014,
2847 .hwcg_reg = 0x45014,
2850 .enable_reg = 0x45014,
2851 .enable_mask = BIT(0),
2860 .halt_reg = 0x45010,
2862 .hwcg_reg = 0x45010,
2865 .enable_reg = 0x45010,
2866 .enable_mask = BIT(0),
2880 .halt_reg = 0x45044,
2882 .hwcg_reg = 0x45044,
2885 .enable_reg = 0x45044,
2886 .enable_mask = BIT(0),
2900 .halt_reg = 0x45078,
2902 .hwcg_reg = 0x45078,
2905 .enable_reg = 0x45078,
2906 .enable_mask = BIT(0),
2920 .halt_reg = 0x4501c,
2923 .enable_reg = 0x4501c,
2924 .enable_mask = BIT(0),
2933 .halt_reg = 0x45018,
2936 .enable_reg = 0x45018,
2937 .enable_mask = BIT(0),
2946 .halt_reg = 0x45040,
2948 .hwcg_reg = 0x45040,
2951 .enable_reg = 0x45040,
2952 .enable_mask = BIT(0),
2966 .halt_reg = 0x1a010,
2969 .enable_reg = 0x1a010,
2970 .enable_mask = BIT(0),
2984 .halt_reg = 0x1a018,
2987 .enable_reg = 0x1a018,
2988 .enable_mask = BIT(0),
3002 .halt_reg = 0x1a014,
3005 .enable_reg = 0x1a014,
3006 .enable_mask = BIT(0),
3015 .halt_reg = 0x9f000,
3018 .enable_reg = 0x9f000,
3019 .enable_mask = BIT(0),
3028 .halt_reg = 0x1a054,
3031 .enable_reg = 0x1a054,
3032 .enable_mask = BIT(0),
3046 .halt_reg = 0x1a058,
3048 .hwcg_reg = 0x1a058,
3051 .enable_reg = 0x1a058,
3052 .enable_mask = BIT(0),
3061 .halt_reg = 0x6e008,
3064 .enable_reg = 0x6e008,
3065 .enable_mask = BIT(0),
3074 .halt_reg = 0x6e010,
3077 .enable_reg = 0x6e010,
3078 .enable_mask = BIT(0),
3087 .halt_reg = 0x6e004,
3090 .enable_reg = 0x6e004,
3091 .enable_mask = BIT(0),
3100 .halt_reg = 0x17004,
3102 .hwcg_reg = 0x17004,
3105 .enable_reg = 0x17004,
3106 .enable_mask = BIT(0),
3115 .halt_reg = 0x1701c,
3117 .hwcg_reg = 0x1701c,
3120 .enable_reg = 0x1701c,
3121 .enable_mask = BIT(0),
3130 .halt_reg = 0x17068,
3132 .hwcg_reg = 0x17068,
3135 .enable_reg = 0x79004,
3145 .halt_reg = 0x580a4,
3147 .hwcg_reg = 0x580a4,
3150 .enable_reg = 0x580a4,
3151 .enable_mask = BIT(0),
3165 .halt_reg = 0x5808c,
3168 .enable_reg = 0x5808c,
3169 .enable_mask = BIT(0),
3183 .halt_reg = 0x17024,
3186 .enable_reg = 0x17024,
3187 .enable_mask = BIT(0),
3196 .gdscr = 0x58004,
3204 .gdscr = 0x45004,
3212 .gdscr = 0x1a004,
3220 .gdscr = 0x58098,
3228 .gdscr = 0x5807c,
3236 .gdscr = 0x7d060,
3245 .gdscr = 0x7d07c,
3254 .gdscr = 0x7d074,
3263 .gdscr = 0x7d078,
3441 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3442 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3443 [GCC_SDCC1_BCR] = { 0x38000 },
3444 [GCC_SDCC2_BCR] = { 0x1e000 },
3445 [GCC_UFS_PHY_BCR] = { 0x45000 },
3446 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3447 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3448 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
3449 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3450 [GCC_VCODEC0_BCR] = { 0x58094 },
3451 [GCC_VENUS_BCR] = { 0x58078 },
3452 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3480 .max_register = 0xc7000,