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/Linux-v5.15/drivers/soc/tegra/fuse/
Dfuse-tegra30.c22 #define FUSE_BEGIN 0x100
25 #define FUSE_VENDOR_CODE 0x100
26 #define FUSE_FAB_CODE 0x104
27 #define FUSE_LOT_CODE_0 0x108
28 #define FUSE_LOT_CODE_1 0x10c
29 #define FUSE_WAFER_ID 0x110
30 #define FUSE_X_COORDINATE 0x114
31 #define FUSE_Y_COORDINATE 0x118
33 #define FUSE_HAS_REVISION_INFO BIT(0)
46 return 0; in tegra30_fuse_read_early()
[all …]
/Linux-v5.15/arch/sh/boards/
Dboard-sh2007.c21 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
22 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
34 [0] = {
36 .end = SMC0_BASE + 0xff,
40 .start = evt2irq(0x240),
41 .end = evt2irq(0x240),
47 [0] = {
49 .end = SMC1_BASE + 0xff,
53 .start = evt2irq(0x280),
54 .end = evt2irq(0x280),
[all …]
/Linux-v5.15/arch/arm/boot/compressed/
Dhead-sharpsl.S29 mov r1, #0x10000000 @ Base address of TC6393 chip
30 mov r6, #0x03
31 ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
36 mrc p15, 0, r4, c0, c0 @ Get Processor ID
37 and r4, r4, #0xffffff00
45 mov r6, #0x31 @ Load Magic Init value
46 str r6, [r1, #0x280] @ to SCRATCH_UMSK
47 mov r5, #0x3000
51 mov r6, #0x30 @ Load 2nd Magic Init value
52 str r6, [r1, #0x280] @ to SCRATCH_UMSK
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/rtc/
Dsprd,sc27xx-rtc.txt10 sc2731_pmic: pmic@0 {
12 reg = <0>;
18 #size-cells = <0>;
22 reg = <0x280>;
/Linux-v5.15/Documentation/devicetree/bindings/reset/
Damlogic,meson-axg-audio-arb.txt19 reg = <0x0 0x280 0x0 0x4>;
/Linux-v5.15/drivers/clk/meson/
Dmeson8b.h16 * Register offsets from the HardKernel[0] data sheet are listed in comment
20 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
23 #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
24 #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
25 #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
26 #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
27 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
29 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
[all …]
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/Linux-v5.15/drivers/crypto/qat/qat_c3xxx/
Dadf_c3xxx_hw_data.h7 #define ADF_C3XXX_PMISC_BAR 0
10 #define ADF_C3XXX_TX_RINGS_MASK 0xFF
14 #define ADF_C3XXX_ACCELERATORS_MASK 0x7
15 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F
17 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
18 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
19 #define ADF_C3XXX_SMIA0_MASK 0xFFFF
20 #define ADF_C3XXX_SMIA1_MASK 0x1
21 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC
23 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
[all …]
/Linux-v5.15/drivers/crypto/qat/qat_c62x/
Dadf_c62x_hw_data.h7 #define ADF_C62X_SRAM_BAR 0
11 #define ADF_C62X_TX_RINGS_MASK 0xFF
15 #define ADF_C62X_ACCELERATORS_MASK 0x1F
16 #define ADF_C62X_ACCELENGINES_MASK 0x3FF
18 #define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
19 #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
20 #define ADF_C62X_SMIA0_MASK 0xFFFF
21 #define ADF_C62X_SMIA1_MASK 0x1
22 #define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
24 #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
[all …]
/Linux-v5.15/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.h7 #define ADF_DH895XCC_SRAM_BAR 0
11 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF
12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
24 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
[all …]
/Linux-v5.15/drivers/net/wireless/ath/ath9k/
Dar9003_aic.h22 #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0
23 #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0
26 #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000
27 #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280
28 #define ATH_AIC_SRAM_CAL_OFFSET 0x140
29 #define ATH_AIC_SRAM_OFFSET 0x00
31 #define ATH_AIC_BT_JUPITER_CTRL 0x66820
32 #define ATH_AIC_BT_AIC_ENABLE 0x02
35 AIC_CAL_STATE_IDLE = 0,
/Linux-v5.15/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-14nm.yaml51 reg = <0x0ae94400 0x200>,
52 <0x0ae94600 0x280>,
53 <0x0ae94a00 0x1e0>;
59 #phy-cells = <0>;
Ddsi-phy-10nm.yaml53 reg = <0x0ae94400 0x200>,
54 <0x0ae94600 0x280>,
55 <0x0ae94a00 0x1e0>;
61 #phy-cells = <0>;
Ddsi-phy-7nm.yaml36 Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
58 reg = <0x0ae94400 0x200>,
59 <0x0ae94600 0x280>,
60 <0x0ae94900 0x260>;
66 #phy-cells = <0>;
/Linux-v5.15/Documentation/fault-injection/
Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_lrc.c25 #define POSTED BIT(0) in set_offsets()
26 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
28 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
29 (((x) >> 2) & 0x7f) in set_offsets()
30 #define END 0 in set_offsets()
43 count = *data & 0x3f; in set_offsets()
56 u32 offset = 0; in set_offsets()
65 regs[0] = base + (offset << 2); in set_offsets()
74 *regs |= BIT(0); in set_offsets()
80 LRI(11, 0),
[all …]
/Linux-v5.15/drivers/soc/renesas/
Dr8a77980-sysc.c17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON },
29 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
30 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
31 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
[all …]
/Linux-v5.15/drivers/media/dvb-frontends/
Ddib0090.c25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
31 } while (0)
40 #define EN_LNA0 0x8000
41 #define EN_LNA1 0x4000
42 #define EN_LNA2 0x2000
43 #define EN_LNA3 0x1000
44 #define EN_MIX0 0x0800
45 #define EN_MIX1 0x0400
46 #define EN_MIX2 0x0200
47 #define EN_MIX3 0x0100
[all …]
/Linux-v5.15/drivers/pinctrl/
Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]
/Linux-v5.15/arch/mips/include/asm/txx9/
Drbtx4927.h32 #define RBTX4927_PCIMEM 0x08000000
33 #define RBTX4927_PCIMEM_SIZE 0x08000000
34 #define RBTX4927_PCIIO 0x16000000
35 #define RBTX4927_PCIIO_SIZE 0x01000000
37 #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
38 #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
39 #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40 #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
41 #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
42 #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/Linux-v5.15/Documentation/staging/
Dstatic-keys.rst236 ffffffff81044294: e9 00 00 00 00 jmpq ffffffff81044299 <sys_getppid+0x9>
237 ffffffff81044299: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax
239 ffffffff810442a2: 48 8b 80 80 02 00 00 mov 0x280(%rax),%rax
240 ffffffff810442a9: 48 8b 80 b0 02 00 00 mov 0x2b0(%rax),%rax
241 ffffffff810442b0: 48 8b b8 e8 02 00 00 mov 0x2e8(%rax),%rdi
246 ffffffff810442c0: 48 c7 c7 e3 54 98 81 mov $0xffffffff819854e3,%rdi
249 ffffffff810442ce: eb c9 jmp ffffffff81044299 <sys_getppid+0x9>
254 …ffffffff810441f0: 8b 05 8a 52 d8 00 mov 0xd8528a(%rip),%eax # ffffffff81dc94…
258 ffffffff810441fc: 75 27 jne ffffffff81044225 <sys_getppid+0x35>
259 ffffffff810441fe: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax
[all …]
/Linux-v5.15/drivers/gpu/drm/bridge/
Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
/Linux-v5.15/arch/arm/mach-imx/
Danatop.c16 #define REG_SET 0x4
17 #define REG_CLR 0x8
19 #define ANADIG_REG_2P5 0x130
20 #define ANADIG_REG_CORE 0x140
21 #define ANADIG_ANA_MISC0 0x150
22 #define ANADIG_DIGPROG 0x260
23 #define ANADIG_DIGPROG_IMX6SL 0x280
24 #define ANADIG_DIGPROG_IMX7D 0x800
26 #define SRC_SBMR2 0x1c
28 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
[all …]

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