Searched +full:0 +full:x20110000 (Results 1 – 6 of 6) sorted by relevance
17 #size-cells = <0>;19 cpu@0 {20 clock-frequency = <0>;26 reg = <0>;38 clock-frequency = <0>;65 clock-frequency = <0>;92 clock-frequency = <0>;119 clock-frequency = <0>;160 reg = <0x0 0x2010000 0x0 0x1000>;165 reg = <0x0 0x2000000 0x0 0xC000>;[all …]
81 pattern: "^cti(@[0-9a-f]+)$"123 const: 0129 '^trig-conns@([0-9]+)$':230 reg = <0x20020000 0x1000>;241 reg = <0x859000 0x1000>;257 reg = <0x858000 0x1000>;265 #size-cells = <0>;267 trig-conns@0 {268 reg = <0>;285 arm,trig-in-sigs = <0 1>;[all …]
87 .start = 0,88 .end = 0,94 .start = 0,95 .end = 0,101 .start = 0,102 .end = 0,108 .start = 0,109 .end = 0,162 #define RAMDISK_IMAGE_START_MASK 0x07FF163 #define RAMDISK_PROMPT_FLAG 0x8000[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x00 0x70000000 0x00 0x200000>;25 ranges = <0x0 0x00 0x70000000 0x200000>;28 reg = <0x1c0000 0x20000>;32 reg = <0x1e0000 0x1c000>;36 reg = <0x1fc000 0x4000>;42 reg = <0x0 0x43000000 0x0 0x20000>;45 ranges = <0x0 0x0 0x43000000 0x20000>;50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */[all …]
17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 025 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF000031 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 033 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF000042 #define PIN_CFG_NA 0x0000000043 #define PIN_CFG_GPIO0_P0 0x0000000144 #define PIN_CFG_GPIO1_P0 0x00000002[all …]
131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3132 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0133 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3164 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0165 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3167 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1287 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0288 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1[all …]
