Lines Matching +full:0 +full:x20110000

131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK	  0x3
132 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT   0
133 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK  0x3F	/* Set 0 */
163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK	0x3
164 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT	0
165 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK		0x3
167 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK		0xF
286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK		0x1
287 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT		0
288 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK		0x1
290 #define CORE_TX_BD_DATA_START_BD_MASK			0x1
292 #define CORE_TX_BD_DATA_IP_CSUM_MASK			0x1
294 #define CORE_TX_BD_DATA_L4_CSUM_MASK			0x1
296 #define CORE_TX_BD_DATA_IPV6_EXT_MASK			0x1
298 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK		0x1
300 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK	0x1
302 #define CORE_TX_BD_DATA_NBDS_MASK			0xF
304 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK			0x1
306 #define CORE_TX_BD_DATA_IP_LEN_MASK			0x1
308 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK	0x1
310 #define CORE_TX_BD_DATA_RESERVED0_MASK			0x1
321 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK		0x3FFF
322 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT	0
323 #define CORE_TX_BD_TX_DST_MASK			0x3
401 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
402 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
403 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK	0x1
405 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK	0x1
407 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
409 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK	0x1
411 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK	0x1
413 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK	0x1
415 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK	0x1
418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK	0x1
419 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT	0
420 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK	0x1
422 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK	0x1
424 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK		0x1
426 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK		0x1
428 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK		0x1
430 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
432 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
435 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
436 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	0
437 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
439 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
441 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
445 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	0
446 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
448 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
450 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
454 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	0
455 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
457 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
459 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK	0x3
462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK	0x3
463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT	0
464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK	0x3
466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK	0x3
468 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK	0x3
471 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK	0x3
472 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT	0
473 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK			0x3
475 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK			0x3
477 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
480 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
481 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
482 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK	0x3
484 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
486 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	0
493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
495 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK	0x1
497 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK	0x1
499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK	0x1
501 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK	0x1
503 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK	0x1
505 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK	0x1
508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK			0x1
509 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT			0
510 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK			0x1
512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK			0x1
514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK			0x1
516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK			0x1
518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK			0x1
520 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK	0x1
522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK			0x1
525 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK		0x1
526 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
527 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
529 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
531 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK		0x1
533 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
535 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK			0x1
537 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK		0x1
539 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK		0x1
542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK	0x1
543 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT	0
544 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK	0x1
546 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
548 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
550 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
552 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
554 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
556 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK		0x1
559 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK	0x1
560 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT	0
561 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK	0x1
563 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
565 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
567 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK	0x1
569 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK	0x1
571 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK	0x1
573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK	0x1
576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK	0x1
577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT	0
578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK	0x1
580 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
582 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
584 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
586 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
593 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK	0x1
594 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT	0
595 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK	0x1
597 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK	0x1
599 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK	0x1
601 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK	0x1
603 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK	0x1
605 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK	0x3
664 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
665 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
666 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
668 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK	0x1
670 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK	0x1
672 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK	0x1
674 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK	0x1
676 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
679 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
680 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	0
681 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
683 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
685 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
689 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	0
690 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
692 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
694 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
698 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	0
699 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK	0x1
703 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK	0x1
705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		0
712 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK		0x1
718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK		0x1
720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK		0x1
722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK		0x1
724 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
727 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
728 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
729 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
731 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
733 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
735 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
737 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
739 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
741 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
768 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
769 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
770 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
772 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
774 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
776 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
779 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
780 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT	0
781 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
783 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
785 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
788 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
789 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
790 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
792 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
794 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK		0x1
796 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
798 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
800 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
802 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
805 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
806 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
807 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
809 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
811 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
813 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
815 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
817 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
819 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
1003 #define EVENT_RING_ENTRY_ASYNC_MASK		0x1
1004 #define EVENT_RING_ENTRY_ASYNC_SHIFT		0
1005 #define EVENT_RING_ENTRY_RESERVED1_MASK		0x7F
1235 	ETH_VER_KEY = 0,
1335 	TUNNEL_CLSS_MAC_VLAN = 0,
1418 #define DMAE_CMD_SRC_MASK		0x1
1419 #define DMAE_CMD_SRC_SHIFT		0
1420 #define DMAE_CMD_DST_MASK		0x3
1422 #define DMAE_CMD_C_DST_MASK		0x1
1424 #define DMAE_CMD_CRC_RESET_MASK		0x1
1426 #define DMAE_CMD_SRC_ADDR_RESET_MASK	0x1
1428 #define DMAE_CMD_DST_ADDR_RESET_MASK	0x1
1430 #define DMAE_CMD_COMP_FUNC_MASK		0x1
1432 #define DMAE_CMD_COMP_WORD_EN_MASK	0x1
1434 #define DMAE_CMD_COMP_CRC_EN_MASK	0x1
1436 #define DMAE_CMD_COMP_CRC_OFFSET_MASK	0x7
1438 #define DMAE_CMD_RESERVED1_MASK		0x1
1440 #define DMAE_CMD_ENDIANITY_MODE_MASK	0x3
1442 #define DMAE_CMD_ERR_HANDLING_MASK	0x3
1444 #define DMAE_CMD_PORT_ID_MASK		0x3
1446 #define DMAE_CMD_SRC_PF_ID_MASK		0xF
1448 #define DMAE_CMD_DST_PF_ID_MASK		0xF
1450 #define DMAE_CMD_SRC_VF_ID_VALID_MASK	0x1
1452 #define DMAE_CMD_DST_VF_ID_VALID_MASK	0x1
1454 #define DMAE_CMD_RESERVED2_MASK		0x3
1462 #define DMAE_CMD_SRC_VF_ID_MASK		0xFF
1463 #define DMAE_CMD_SRC_VF_ID_SHIFT	0
1464 #define DMAE_CMD_DST_VF_ID_MASK		0xFF
1475 #define DMAE_CMD_ERROR_BIT_MASK        0x1
1476 #define DMAE_CMD_ERROR_BIT_SHIFT       0
1477 #define DMAE_CMD_RESERVED_MASK	       0x7FFF
1532 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1533 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1534 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1536 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1538 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1540 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1543 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1544 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1545 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1547 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1549 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1551 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1553 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1555 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1557 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1569 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1570 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1571 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1573 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1575 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1577 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1580 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1581 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1582 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1584 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1586 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1588 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1590 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1592 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1594 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1619 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK	0x1
1620 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT	0
1621 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK	0x1
1623 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK	0x1
1625 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK	0x1
1627 #define QED_DMAE_PARAMS_PORT_VALID_MASK		0x1
1629 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK	0x1
1631 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK	0x1
1633 #define QED_DMAE_PARAMS_RESERVED_MASK		0x1FFFFFF
1647 #define IGU_CLEANUP_RESERVED0_MASK	0x7FFFFFF
1648 #define IGU_CLEANUP_RESERVED0_SHIFT	0
1649 #define IGU_CLEANUP_CLEANUP_SET_MASK	0x1
1651 #define IGU_CLEANUP_CLEANUP_TYPE_MASK	0x7
1653 #define IGU_CLEANUP_COMMAND_TYPE_MASK	0x1
1668 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK	0xFFF
1669 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT	0
1670 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK	0x7
1672 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK	0x1
1679 #define IGU_MAPPING_LINE_VALID_MASK		0x1
1680 #define IGU_MAPPING_LINE_VALID_SHIFT		0
1681 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK	0xFF
1683 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK	0xFF
1685 #define IGU_MAPPING_LINE_PF_VALID_MASK		0x1
1687 #define IGU_MAPPING_LINE_IPS_GROUP_MASK		0x3F
1689 #define IGU_MAPPING_LINE_RESERVED_MASK		0xFF
1698 #define IGU_MSIX_VECTOR_MASK_BIT_MASK		0x1
1699 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT		0
1700 #define IGU_MSIX_VECTOR_RESERVED0_MASK		0x7FFF
1702 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK	0xFF
1704 #define IGU_MSIX_VECTOR_RESERVED1_MASK		0xFF
1710 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK		0x1
1711 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT		0
1712 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK		0x1
1714 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK			0x1
1716 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK			0x1
1718 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK	0x1
1720 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK	0x1
1722 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK			0x3
1737 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK		0x1
1738 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT		0
1739 #define QM_RF_BYPASS_MASK_RESERVED0_MASK	0x1
1741 #define QM_RF_BYPASS_MASK_PFWFQ_MASK		0x1
1743 #define QM_RF_BYPASS_MASK_VPWFQ_MASK		0x1
1745 #define QM_RF_BYPASS_MASK_PFRL_MASK		0x1
1747 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK		0x1
1749 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK		0x1
1751 #define QM_RF_BYPASS_MASK_RESERVED1_MASK	0x1
1758 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK		0x1
1759 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT		0
1760 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK		0x1
1762 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK		0x1
1764 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK		0x1
1766 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK		0x1
1768 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK		0x1
1770 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK		0x1
1772 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK		0x1
1774 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK	0x1
1776 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK		0x7F
1783 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK		0x1
1784 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT		0
1785 #define QM_RF_PQ_MAP_E4_RL_ID_MASK		0xFF
1787 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK		0x1FF
1789 #define QM_RF_PQ_MAP_E4_VOQ_MASK		0x1F
1791 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK	0x3
1793 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK		0x1
1795 #define QM_RF_PQ_MAP_E4_RESERVED_MASK		0x3F
1802 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK	0x3F
1803 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT	0
1804 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK	0x1
1806 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK	0x1FF
1813 #define SDM_OP_GEN_COMP_PARAM_MASK	0xFFFF
1814 #define SDM_OP_GEN_COMP_PARAM_SHIFT	0
1815 #define SDM_OP_GEN_COMP_TYPE_MASK	0xF
1817 #define SDM_OP_GEN_RESERVED_MASK	0xFFF
1962 #define DBG_ATTN_BIT_MAPPING_VAL_MASK			0x7FFF
1963 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT			0
1964 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK	0x1
1986 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK	0xFFFFFF
1987 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT	0
1988 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK	0xFF
2000 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK	0x3
2001 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT	0
2002 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK	0x3F
2011 #define DBG_MODE_HDR_EVAL_MODE_MASK		0x1
2012 #define DBG_MODE_HDR_EVAL_MODE_SHIFT		0
2013 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK	0x7FFF
2022 #define DBG_ATTN_REG_STS_ADDRESS_MASK	0xFFFFFF
2023 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT	0
2024 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK	0xFF
2046 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK		 0x1
2047 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT		 0
2048 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK	 0x1
2050 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK  0x1
2052 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK		 0x1
2054 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK	 0x1
2056 #define DBG_BLOCK_CHIP_RESERVED0_MASK		 0x7
2088 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK		0xF
2089 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT	0
2090 #define DBG_BUS_LINE_IS_256B_MASK		0x1
2092 #define DBG_BUS_LINE_RESERVED_MASK		0x7
2107 #define DBG_DUMP_MEM_ADDRESS_MASK	0xFFFFFF
2108 #define DBG_DUMP_MEM_ADDRESS_SHIFT	0
2109 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK	0xFF
2112 #define DBG_DUMP_MEM_LENGTH_MASK	0xFFFFFF
2113 #define DBG_DUMP_MEM_LENGTH_SHIFT	0
2114 #define DBG_DUMP_MEM_WIDE_BUS_MASK	0x1
2116 #define DBG_DUMP_MEM_RESERVED_MASK	0x7F
2123 #define DBG_DUMP_REG_ADDRESS_MASK	0x7FFFFF
2124 #define DBG_DUMP_REG_ADDRESS_SHIFT	0
2125 #define DBG_DUMP_REG_WIDE_BUS_MASK	0x1
2127 #define DBG_DUMP_REG_LENGTH_MASK	0xFF
2134 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK	0xFFFFFF
2135 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT	0
2136 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK	0xFF
2149 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK	0x7FFFFF
2150 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT	0
2151 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK	0x1
2153 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK	0xFF
2163 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK	0x7FFFFF
2164 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT	0
2165 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK	0x1
2167 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK	0xFF
2192 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
2193 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2194 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
2220 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK	0x1
2221 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT	0
2222 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK	0x7FFFFFFF
2240 #define DBG_RESET_REG_ADDR_MASK        0xFFFFFF
2241 #define DBG_RESET_REG_ADDR_SHIFT       0
2242 #define DBG_RESET_REG_IS_REMOVED_MASK  0x1
2244 #define DBG_RESET_REG_RESERVED_MASK    0x7F
2258 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK  0x1
2259 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
2260 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK      0x7F
2685 #define ANY_PHASE_ID	0xffff
2789 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK  0xFF
2790 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2791 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK  0xFFFFFF
2798 #define INIT_ARRAY_RAW_HDR_TYPE_MASK			0xF
2799 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT			0
2800 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK			0xFFFFFFF
2807 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK		0xF
2808 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT		0
2809 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK		0xFFFFFFF
2816 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK			0xF
2817 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT		0
2818 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK		0xFFFFFFF
2825 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK		0xF
2826 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT		0
2827 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK	0xF
2829 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK		0xFFFFFF
2852 #define INIT_CALLBACK_OP_OP_MASK			0xF
2853 #define INIT_CALLBACK_OP_OP_SHIFT			0
2854 #define INIT_CALLBACK_OP_RESERVED_MASK			0xFFFFFFF
2863 #define INIT_DELAY_OP_OP_MASK				0xF
2864 #define INIT_DELAY_OP_OP_SHIFT				0
2865 #define INIT_DELAY_OP_RESERVED_MASK			0xFFFFFFF
2873 #define INIT_IF_MODE_OP_OP_MASK				0xF
2874 #define INIT_IF_MODE_OP_OP_SHIFT			0
2875 #define INIT_IF_MODE_OP_RESERVED1_MASK			0xFFF
2877 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK			0xFFFF
2886 #define INIT_IF_PHASE_OP_OP_MASK			0xF
2887 #define INIT_IF_PHASE_OP_OP_SHIFT			0
2888 #define INIT_IF_PHASE_OP_RESERVED1_MASK			0xFFF
2890 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK		0xFFFF
2893 #define INIT_IF_PHASE_OP_PHASE_MASK			0xFF
2894 #define INIT_IF_PHASE_OP_PHASE_SHIFT			0
2895 #define INIT_IF_PHASE_OP_RESERVED2_MASK			0xFF
2897 #define INIT_IF_PHASE_OP_PHASE_ID_MASK			0xFFFF
2912 #define INIT_RAW_OP_OP_MASK				0xF
2913 #define INIT_RAW_OP_OP_SHIFT				0
2914 #define INIT_RAW_OP_PARAM1_MASK				0xFFFFFFF
2936 #define INIT_WRITE_OP_OP_MASK				0xF
2937 #define INIT_WRITE_OP_OP_SHIFT				0
2938 #define INIT_WRITE_OP_SOURCE_MASK			0x7
2940 #define INIT_WRITE_OP_RESERVED_MASK			0x1
2942 #define INIT_WRITE_OP_WIDE_BUS_MASK			0x1
2944 #define INIT_WRITE_OP_ADDRESS_MASK			0x7FFFFF
2952 #define INIT_READ_OP_OP_MASK				0xF
2953 #define INIT_READ_OP_OP_SHIFT				0
2954 #define INIT_READ_OP_POLL_TYPE_MASK			0xF
2956 #define INIT_READ_OP_RESERVED_MASK			0x1
2958 #define INIT_READ_OP_ADDRESS_MASK			0x7FFFFF
3385 #define MCP_TRACE_FORMAT_MODULE_MASK	0x0000ffff
3386 #define MCP_TRACE_FORMAT_MODULE_OFFSET	0
3387 #define MCP_TRACE_FORMAT_LEVEL_MASK	0x00030000
3389 #define MCP_TRACE_FORMAT_P1_SIZE_MASK	0x000c0000
3391 #define MCP_TRACE_FORMAT_P2_SIZE_MASK	0x00300000
3393 #define MCP_TRACE_FORMAT_P3_SIZE_MASK	0x00c00000
3395 #define MCP_TRACE_FORMAT_LEN_MASK	0xff000000
3713 #define GTT_BAR0_MAP_REG_IGU_CMD	0x00f000UL
3716 #define GTT_BAR0_MAP_REG_TSDM_RAM	0x010000UL
3719 #define GTT_BAR0_MAP_REG_MSDM_RAM	0x011000UL
3722 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024	0x012000UL
3725 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048	0x013000UL
3728 #define GTT_BAR0_MAP_REG_USDM_RAM	0x014000UL
3731 #define GTT_BAR0_MAP_REG_USDM_RAM_1024	0x015000UL
3734 #define GTT_BAR0_MAP_REG_USDM_RAM_2048	0x016000UL
3737 #define GTT_BAR0_MAP_REG_XSDM_RAM	0x017000UL
3740 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024	0x018000UL
3743 #define GTT_BAR0_MAP_REG_YSDM_RAM	0x019000UL
3746 #define GTT_BAR0_MAP_REG_PSDM_RAM	0x01a000UL
3810  * @return 0 on success, -1 on error.
3823  * @return 0 on success, -1 on error.
3838  * @return 0 on success, -1 on error.
3853  * @return 0 on success, -1 on error.
3996  * @brief qed_memset_session_ctx - Memset session context to 0 while
4007  * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4068 #define YSTORM_FLOW_CONTROL_MODE_OFFSET			(IRO[0].base)
4069 #define YSTORM_FLOW_CONTROL_MODE_SIZE			(IRO[0].size)
4396 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET				0
4836 #define DMAE_READY_CB	0
4857 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
4858 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
4859 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK	0x1
4861 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK	0x1
4863 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
4865 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK	0x1
4867 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK	0x1
4869 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK	0x1
4871 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK	0x1
4874 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK	0x1
4875 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT	0
4876 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK	0x1
4878 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK	0x1
4880 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK		0x1
4882 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
4884 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
4886 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
4888 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
4891 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
4892 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	0
4893 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
4895 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
4897 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
4900 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
4901 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	0
4902 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
4904 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
4906 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
4909 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
4910 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	0
4911 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
4913 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
4915 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK	0x3
4918 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK	0x3
4919 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT	0
4920 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK	0x3
4922 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK	0x3
4924 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK	0x3
4927 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK		0x3
4928 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
4929 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK		0x3
4931 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK			0x3
4933 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
4936 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
4937 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
4938 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK	0x3
4940 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK	0x3
4942 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK		0x1
4944 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK		0x1
4947 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
4948 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	0
4949 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
4951 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
4953 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
4955 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
4957 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
4959 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
4961 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
4964 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK			0x1
4965 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT			0
4966 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK			0x1
4968 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK			0x1
4970 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK			0x1
4972 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK			0x1
4974 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK			0x1
4976 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
4978 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
4981 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
4982 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
4983 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
4985 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
4987 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK		0x1
4989 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
4991 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
4993 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK		0x1
4995 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK		0x1
4998 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK	0x1
4999 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT	0
5000 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK	0x1
5002 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
5004 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
5006 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK		0x1
5008 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
5010 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
5012 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK		0x1
5015 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK		0x1
5016 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT	0
5017 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK		0x1
5019 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
5021 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
5023 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK		0x1
5025 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK		0x1
5027 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK		0x1
5029 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK		0x1
5032 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK		0x1
5033 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT	0
5034 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK		0x1
5036 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
5038 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
5040 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
5042 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
5044 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
5046 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
5049 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK		0x1
5050 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
5051 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
5053 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
5055 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
5057 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK		0x1
5059 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK		0x1
5061 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
5125 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
5126 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
5127 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
5129 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
5131 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK		0x3
5133 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
5136 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
5137 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	0
5138 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK	0x1
5140 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
5142 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
5144 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK			0x1
5146 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK			0x1
5148 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK			0x1
5150 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK			0x1
5169 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK	0x1
5170 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT	0
5171 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK	0x1
5173 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK	0x1
5175 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK	0x1
5177 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK	0x1
5179 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK	0x1
5181 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
5184 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
5185 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	0
5186 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
5188 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
5190 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
5193 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
5194 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	0
5195 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
5197 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
5199 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
5202 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
5203 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	0
5204 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
5206 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
5208 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
5210 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
5212 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
5215 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
5216 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	0
5217 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
5219 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
5221 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
5223 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
5225 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
5227 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK	0x1
5229 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
5232 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK		0x1
5233 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT		0
5234 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK		0x1
5236 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK		0x1
5238 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK		0x1
5240 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
5242 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK		0x1
5244 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
5246 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK		0x1
5273 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
5274 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
5275 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
5277 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK	0x3
5279 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK	0x3
5281 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
5284 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK			0x3
5285 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT			0
5286 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK		0x3
5288 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK		0x3
5290 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
5293 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK	0x1
5294 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT	0
5295 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK	0x1
5297 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
5299 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK			0x1
5301 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK		0x1
5303 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK		0x1
5305 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
5307 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
5310 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
5311 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	0
5312 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
5314 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
5316 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
5318 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK	0x1
5320 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK	0x1
5322 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK	0x1
5324 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK	0x1
5365 	ETH_OK = 0x00,
5528 #define ETH_RETURN_CODE_ERR_CODE_MASK  0x3F
5529 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5530 #define ETH_RETURN_CODE_RESERVED_MASK  0x1
5532 #define ETH_RETURN_CODE_RX_TX_MASK     0x1
5554 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK			0x1
5555 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT			0
5556 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK			0x1
5558 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK			0x1
5560 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK		0x1
5562 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK	0x1
5564 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK			0x1
5566 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK		0x1
5568 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK			0x1
5570 #define ETH_TX_ERR_VALS_RESERVED_MASK				0xFF
5577 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK		0x1
5578 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT		0
5579 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK		0x1
5581 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK		0x1
5583 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK		0x1
5585 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK		0x1
5587 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK		0x1
5589 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK		0x1
5591 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK			0x1FF
5615 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK		0x1
5616 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT		0
5617 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
5619 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK	0x1
5621 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK		0x1
5623 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
5625 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
5627 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK		0x1
5629 #define ETH_VPORT_RX_MODE_RESERVED1_MASK		0x1FF
5656 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK		0x1
5657 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT		0
5658 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
5660 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK		0x1
5662 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
5664 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
5666 #define ETH_VPORT_TX_MODE_RESERVED1_MASK		0x7FF
5811 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK	0x1
5812 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT	0
5813 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK	0x1
5815 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK		0x1
5817 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK		0x1
5819 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK		0x1
5821 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK		0x7
5971 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
5972 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
5973 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK		0x1
5975 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK		0x1
5977 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
5979 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK		0x1
5981 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK		0x1
5983 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK		0x1
5985 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK		0x1
5988 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK		0x1
5989 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT		0
5990 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK		0x1
5992 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK		0x1
5994 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
5996 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK	0x1
5998 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK	0x1
6000 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK	0x1
6002 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK	0x1
6005 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK	0x3
6006 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT	0
6007 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK	0x3
6009 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK	0x3
6011 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK	0x3
6014 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK	0x3
6015 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT	0
6016 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK	0x3
6018 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK	0x3
6020 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK	0x3
6023 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK	0x3
6024 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT	0
6025 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK	0x3
6027 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK	0x3
6029 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK	0x3
6032 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK	0x3
6033 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT	0
6034 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK	0x3
6036 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK	0x3
6038 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK	0x3
6041 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK	0x3
6042 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT	0
6043 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK	0x3
6045 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK		0x3
6047 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK	0x3
6050 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK		0x3
6051 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT		0
6052 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK		0x3
6054 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
6056 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
6058 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
6061 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK	0x1
6062 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT	0
6063 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK	0x1
6065 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK	0x1
6067 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK	0x1
6069 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK	0x1
6071 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK	0x1
6073 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK	0x1
6075 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK	0x1
6078 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK			0x1
6079 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT			0
6080 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK			0x1
6082 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK			0x1
6084 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK			0x1
6086 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK			0x1
6088 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK			0x1
6090 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK	0x1
6092 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK	0x1
6095 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK			0x1
6096 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT			0
6097 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK		0x1
6099 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK		0x1
6101 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK			0x1
6103 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK		0x1
6105 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK	0x1
6107 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK			0x1
6109 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK			0x1
6112 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK		0x1
6113 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT	0
6114 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK		0x1
6116 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK	0x1
6118 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
6120 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
6122 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
6124 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
6126 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
6129 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
6131 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
6133 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
6135 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
6137 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
6139 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
6141 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
6143 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
6147 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
6148 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
6150 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
6152 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
6154 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
6156 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
6158 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
6160 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK		0x1
6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT		0
6165 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK		0x1
6167 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK	0x1
6169 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK	0x1
6171 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK		0x1
6173 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK		0x1
6175 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK			0x3
6200 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6201 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	 0
6202 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK		0x1
6204 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK		0x3
6206 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK		0x3
6208 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK		0x3
6211 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
6212 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	0
6213 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
6215 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
6217 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
6219 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
6221 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
6223 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
6225 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
6237 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6238 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
6239 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK	0x1
6241 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK	0x1
6243 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
6245 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK	0x1
6247 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK	0x1
6249 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK	0x1
6251 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK	0x1
6254 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK		0x1
6255 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT		0
6256 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK		0x1
6258 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK		0x1
6260 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK			0x1
6262 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK		0x1
6264 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK		0x1
6266 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
6268 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK		0x1
6271 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK	0x3
6272 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT	0
6273 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK	0x3
6275 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK	0x3
6277 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK	0x3
6280 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK	0x3
6281 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT	0
6282 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK	0x3
6284 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK	0x3
6286 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK	0x3
6289 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK	0x3
6290 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT	0
6291 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK	0x3
6293 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK	0x3
6295 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK	0x3
6298 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK	0x3
6299 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT	0
6300 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK	0x3
6302 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK	0x3
6304 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK	0x3
6307 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK	0x3
6308 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
6309 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK	0x3
6311 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK			0x3
6313 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
6316 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
6317 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
6318 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK	0x3
6320 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK	0x3
6322 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK		0x1
6324 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK		0x1
6327 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK		0x1
6328 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT	0
6329 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK		0x1
6331 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK		0x1
6333 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK		0x1
6335 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK		0x1
6337 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK		0x1
6339 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK		0x1
6341 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK		0x1
6344 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK		0x1
6345 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT		0
6346 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK		0x1
6348 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK		0x1
6350 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK		0x1
6352 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK		0x1
6354 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK		0x1
6356 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
6358 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
6361 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
6362 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT			0
6363 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
6365 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK			0x1
6367 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK			0x1
6369 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
6371 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
6373 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK			0x1
6375 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK			0x1
6378 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK		0x1
6379 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT		0
6380 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK		0x1
6382 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
6384 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK		0x1
6386 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK		0x1
6388 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK		0x1
6390 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
6392 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK		0x1
6395 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK	0x1
6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT	0
6397 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK	0x1
6399 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
6401 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
6403 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK	0x1
6405 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK	0x1
6407 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK	0x1
6409 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK	0x1
6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK	0x1
6413 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT	0
6414 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK	0x1
6416 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
6418 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
6420 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
6422 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
6424 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
6426 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK	0x1
6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
6431 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
6433 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
6435 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
6437 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK	0x1
6439 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
6441 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
6456 #define GFT_CAM_LINE_MAPPED_VALID_MASK				0x1
6457 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT				0
6458 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK			0x1
6460 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK		0x1
6462 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK		0xF
6464 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK			0xF
6466 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK				0xF
6468 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK		0x1
6470 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK		0x1
6472 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK	0xF
6474 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK		0xF
6476 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK			0xF
6478 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK			0x7
6485 	GFT_PROFILE_IPV4 = 0,
6493 #define GFT_PROFILE_KEY_IP_VERSION_MASK			0x1
6494 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT		0
6495 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK		0x1
6497 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK	0xF
6499 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK		0xF
6501 #define GFT_PROFILE_KEY_PF_ID_MASK			0xF
6503 #define GFT_PROFILE_KEY_RESERVED0_MASK			0x3
6509 	GFT_PROFILE_NO_TUNNEL = 0,
6520 	GFT_PROFILE_ROCE_PROTOCOL = 0,
6542 #define GFT_RAM_LINE_VLAN_SELECT_MASK			0x3
6543 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT			0
6544 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK		0x1
6546 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK		0x1
6548 #define GFT_RAM_LINE_TUNNEL_TTL_MASK			0x1
6550 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK		0x1
6552 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK		0x1
6554 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK		0x1
6556 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK			0x1
6558 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK	0x1
6560 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK			0x1
6562 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK			0x1
6564 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK		0x1
6566 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK		0x1
6568 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK			0x1
6570 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK		0x1
6572 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK		0x1
6574 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK			0x1
6576 #define GFT_RAM_LINE_TTL_MASK				0x1
6578 #define GFT_RAM_LINE_ETHERTYPE_MASK			0x1
6580 #define GFT_RAM_LINE_RESERVED0_MASK			0x1
6582 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK			0x1
6584 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK			0x1
6586 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK			0x1
6588 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK			0x1
6590 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK			0x1
6592 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK			0x1
6594 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK			0x1
6596 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK			0x1
6598 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK			0x1
6600 #define GFT_RAM_LINE_DST_PORT_MASK			0x1
6602 #define GFT_RAM_LINE_SRC_PORT_MASK			0x1
6605 #define GFT_RAM_LINE_DSCP_MASK				0x1
6606 #define GFT_RAM_LINE_DSCP_SHIFT				0
6607 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK		0x1
6609 #define GFT_RAM_LINE_DST_IP_MASK			0x1
6611 #define GFT_RAM_LINE_SRC_IP_MASK			0x1
6613 #define GFT_RAM_LINE_PRIORITY_MASK			0x1
6615 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK			0x1
6617 #define GFT_RAM_LINE_VLAN_MASK				0x1
6619 #define GFT_RAM_LINE_DST_MAC_MASK			0x1
6621 #define GFT_RAM_LINE_SRC_MAC_MASK			0x1
6623 #define GFT_RAM_LINE_TENANT_ID_MASK			0x1
6625 #define GFT_RAM_LINE_RESERVED1_MASK			0x3FFFFF
6631 	INNER_PROVIDER_VLAN = 0,
6648 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6649 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6650 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6652 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6654 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK			0x1
6656 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
6659 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK		0x3
6660 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT		0
6661 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK		0x3
6663 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK	0x3
6665 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK		0x1
6667 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK		0x1
6670 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK		0x1
6671 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT		0
6672 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6674 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6676 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
6678 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
6680 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
6682 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
6684 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
6704 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6705 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6706 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6708 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6710 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK			0x1
6712 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
6715 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
6716 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	0
6717 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
6719 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
6721 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
6723 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
6726 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK		0x1
6727 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT		0
6728 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6730 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6732 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
6734 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
6736 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
6738 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
6740 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
6770 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6771 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6772 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6774 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6776 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK	0x3
6779 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK	0x3
6780 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT	0
6781 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK		0x3
6783 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK          0x3
6785 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK		0x3
6788 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK	0x1
6789 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT	0
6790 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK		0x1
6792 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK		0x1
6794 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK               0x1
6796 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK		0x1
6798 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK			0x1
6800 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK			0x1
6802 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK			0x1
6805 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK	0x1
6806 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT	0
6807 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK			0x1
6809 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK	0x1
6811 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK			0x1
6813 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK		0xF
6877 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK  0x1
6878 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6879 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK    0x7F
6919 	RDMA_RETURN_OK = 0,
6969 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK	0x1F
6970 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT	0
6971 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK	0x1
6973 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK		0x1
6975 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK		0x1
6977 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK		0x1
6979 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK		0x1
6981 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK	0x1
6983 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK		0x1
6985 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK		0x1
6987 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK	0x1
6989 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK		0x3
6992 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK	0x1F
6993 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT	0
6994 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK		0x7
6997 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK		0x1
6998 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT		0
6999 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK	0x1
7001 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK		0x3F
7027 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK		0x1
7028 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT		0
7029 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK	0x1
7031 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK		0x1
7033 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK		0x1F
7052 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK         0x1
7053 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT        0
7054 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK  0x1
7056 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK        0x3F
7101 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK		0xF
7102 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT	0
7103 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK		0x1
7105 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK		0x1
7107 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK		0x1
7109 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK		0x1
7112 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK	0x1
7113 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT	0
7114 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK	0x1
7116 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
7118 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
7120 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
7123 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK	0x3
7124 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT	0
7125 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK	0x3
7127 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK	0x3
7129 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK	0x3
7132 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK	0x3
7133 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT	0
7134 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
7136 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
7138 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK	0x1
7140 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK	0x1
7142 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK	0x1
7144 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK	0x1
7147 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK		0x1
7148 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT		0
7149 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK		0x1
7151 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
7153 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
7155 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
7157 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
7159 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
7161 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
7179 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
7180 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
7181 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK  0x1
7183 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
7185 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK		0x3
7187 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK		0x3
7190 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK		0x3
7191 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT		0
7192 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
7194 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
7196 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK		0x3
7199 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
7200 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
7201 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK			0x1
7203 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK			0x1
7205 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK			0x1
7207 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK		0x1
7209 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
7211 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK			0x1
7213 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
7216 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK		0x1
7217 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT		0
7218 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK		0x1
7220 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK		0x1
7222 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK		0x1
7224 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK		0x1
7226 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK		0x1
7228 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK		0x1
7230 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK		0x1
7248 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
7249 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
7250 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK              0x1
7252 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK              0x1
7254 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
7256 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK              0x1
7258 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK              0x1
7260 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK              0x1
7262 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK              0x1
7265 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK              0x1
7266 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT             0
7267 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK              0x1
7269 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK             0x1
7271 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK             0x1
7273 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK        0x1
7275 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK        0x1
7277 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK	       0x1
7279 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
7282 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK               0x3
7283 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT              0
7284 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK               0x3
7286 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK               0x3
7288 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK               0x3
7291 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK               0x3
7292 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT              0
7293 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK               0x3
7295 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK               0x3
7297 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
7300 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK               0x3
7301 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT              0
7302 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK               0x3
7304 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK              0x3
7306 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK              0x3
7309 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK              0x3
7310 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT             0
7311 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK              0x3
7313 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK              0x3
7315 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK              0x3
7318 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK              0x3
7319 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT             0
7320 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK              0x3
7322 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK              0x3
7324 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK              0x3
7327 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK              0x3
7328 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT             0
7329 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK              0x3
7331 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK         0x3
7333 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK             0x1
7335 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK             0x1
7338 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK             0x1
7339 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT            0
7340 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK             0x1
7342 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK             0x1
7344 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK             0x1
7346 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK             0x1
7348 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
7350 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK             0x1
7352 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK             0x1
7355 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK            0x1
7356 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT           0
7357 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK            0x1
7359 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK            0x1
7361 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK            0x1
7363 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK            0x1
7365 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK            0x1
7367 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK            0x1
7369 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK            0x1
7372 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK            0x1
7373 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT           0
7374 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK            0x1
7376 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK            0x1
7378 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK            0x1
7380 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
7382 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK            0x1
7384 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK           0x1
7386 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK           0x1
7389 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK           0x1
7390 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT          0
7391 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK           0x1
7393 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK           0x1
7395 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK           0x1
7397 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK           0x1
7399 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK           0x1
7401 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
7403 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK           0x1
7406 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK          0x1
7407 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT         0
7408 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK          0x1
7410 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
7412 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
7414 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK          0x1
7416 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK          0x1
7418 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK          0x1
7420 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK          0x1
7423 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK          0x1
7424 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT         0
7425 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK          0x1
7427 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
7429 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
7431 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
7433 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
7435 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
7437 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
7440 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK         0x1
7441 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT        0
7442 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK             0x1
7444 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3
7446 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK          0x1
7448 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1
7450 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK              0x3
7477 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1
7478 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
7479 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK                  0x1
7481 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK                  0x1
7483 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK                  0x1
7485 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK                  0x1
7487 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK                  0x1
7489 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK                   0x3
7492 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3
7493 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
7494 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK                   0x3
7496 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3
7498 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3
7501 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK                   0x3
7502 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT                  0
7503 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK                   0x3
7505 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK                   0x3
7507 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK                   0x3
7510 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK                   0x3
7511 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT                  0
7512 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK                  0x3
7514 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK                 0x1
7516 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1
7518 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK                 0x1
7520 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1
7523 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1
7524 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
7525 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK                 0x1
7527 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK                 0x1
7529 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK                 0x1
7531 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK                 0x1
7533 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK                 0x1
7535 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK                0x1
7537 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK               0x1
7540 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK               0x1
7541 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT              0
7542 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK               0x1
7544 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK               0x1
7546 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK               0x1
7548 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK               0x1
7550 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK               0x1
7552 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK               0x1
7554 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK               0x1
7638 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK			0x3
7639 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
7640 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK		0x1
7642 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
7644 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
7646 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK			0x1
7648 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK		0xF
7650 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK			0xF
7680 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK			0x1
7681 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT			0
7682 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK			0x1
7684 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK			0x3F
7695 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK		0x3
7696 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
7697 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
7699 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
7701 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
7703 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK			0x1
7705 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK	0x1
7707 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK		0x1
7709 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK			0x7
7711 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK		0x1F
7713 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK             0x1
7715 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK	0x1
7717 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK		0x3FFF
7828 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK		0x1
7829 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT		0
7830 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK		0x1
7832 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK		0x3F
7849 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
7850 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
7851 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK		0x1
7853 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK		0x1
7855 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK			0x1
7857 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
7859 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK			0x1
7861 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK		0x1
7863 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK		0x1
7865 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK		0x1
7867 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK			0x1
7869 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
7871 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK		0x1
7873 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK			0x3
7876 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK	0xF
7877 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT	0
7878 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK		0xF
7898 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
7899 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
7900 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
7902 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
7904 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
7906 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK			0x1
7908 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
7910 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK		0x1
7912 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK			0x1
7914 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK	0x1
7916 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK		0x1
7918 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK		0x1
7920 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK			0x1F
7923 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK		0x7
7924 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT		0
7925 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK	0x1F
7944 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK		0x1
7945 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT		0
7946 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK	0x1
7948 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK		0x3FFFFFFF
7961 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
7962 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7963 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
7989 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK	0x1
7990 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT	0
7991 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK	0x1
7993 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK		0x3FFF
8002 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
8003 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
8004 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK		0x1
8006 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK		0x1
8008 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
8010 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK		0x1
8012 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK		0x1
8014 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK		0x1
8016 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK		0x1
8019 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK		0x1
8020 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT		0
8021 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK		0x1
8023 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK		0x1
8025 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
8027 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK	0x1
8029 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK	0x1
8031 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK		0x1
8033 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK	0x1
8036 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK	0x3
8037 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT	0
8038 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK	0x3
8040 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK	0x3
8042 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK	0x3
8045 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK		0x3
8046 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT		0
8047 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK		0x3
8049 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK		0x3
8051 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK	0x3
8054 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK	0x3
8055 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT	0
8056 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK	0x3
8058 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK	0x3
8060 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK	0x3
8063 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK	0x3
8064 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT	0
8065 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK	0x3
8067 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK	0x3
8069 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK	0x3
8072 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK	0x3
8073 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT	0
8074 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK	0x3
8076 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK	0x3
8078 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK	0x3
8081 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK		0x3
8082 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT		0
8083 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK		0x3
8085 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
8087 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
8089 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
8092 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK		0x1
8093 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT		0
8094 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK		0x1
8096 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK		0x1
8098 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK		0x1
8100 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK		0x1
8102 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK	0x1
8104 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK		0x1
8106 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK		0x1
8109 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK	0x1
8110 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT	0
8111 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK	0x1
8113 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK	0x1
8115 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK	0x1
8117 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK	0x1
8119 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK	0x1
8121 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK	0x1
8123 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK	0x1
8126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK		0x1
8127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT		0
8128 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK		0x1
8130 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK		0x1
8132 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK		0x1
8134 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK	0x1
8136 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK		0x1
8138 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK		0x1
8140 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK		0x1
8143 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK		0x1
8144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT		0
8145 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK		0x1
8147 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK		0x1
8149 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
8151 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
8153 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
8155 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
8157 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
8160 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
8161 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
8162 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
8164 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
8166 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
8168 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
8170 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
8172 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
8174 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
8177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
8178 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
8179 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
8181 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
8183 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
8185 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
8187 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
8189 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
8191 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
8194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK		0x1
8195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT	0
8196 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK		0x1
8198 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK	0x3
8200 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK		0x1
8202 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK	0x1
8204 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK		0x3
8229 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
8230 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
8231 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
8233 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
8235 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
8237 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
8240 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
8241 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
8242 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
8244 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
8246 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
8248 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
8250 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
8252 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
8254 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
8266 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8267 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8268 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8270 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8272 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8274 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8277 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8278 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8279 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8281 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8283 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8285 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8287 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8289 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8291 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8303 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8304 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8305 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8307 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8309 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8311 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8314 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8315 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8316 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8318 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8320 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8322 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8324 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8326 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8328 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8340 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
8341 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
8342 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK		0x1
8344 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK	0x1
8346 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK			0x1
8348 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
8350 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK			0x1
8352 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK			0x3
8355 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3
8356 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
8357 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK			0x3
8359 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK		0x3
8361 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK			0x3
8364 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK               0x3
8365 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT              0
8366 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK	0x3
8368 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK	0x3
8370 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK	0x3
8373 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK	0x3
8374 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT	0
8375 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK	0x3
8377 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK			0x1
8379 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
8381 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK		0x1
8383 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
8386 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
8387 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
8388 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK            0x1
8390 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK		0x1
8392 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK	0x1
8394 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK		0x1
8396 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK	0x1
8398 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK	0x1
8400 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK			0x1
8403 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
8404 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		0
8405 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK		0x1
8407 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
8409 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
8411 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
8413 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK	0x1
8415 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK		0x1
8417 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK		0x1
8444 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
8445 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
8446 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK	0x1
8448 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK			0x1
8450 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK			0x1
8452 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
8454 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK			0x1
8456 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK			0x3
8459 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK            0x3
8460 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT           0
8461 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK	0x3
8463 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK		0x3
8465 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
8468 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3
8469 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
8470 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK		0x3
8472 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK		0x3
8474 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK		0x3
8477 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK		0x3
8478 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT		0
8479 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK		0x3
8481 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK		0x1
8483 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1
8485 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK	0x1
8487 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
8490 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
8491 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
8492 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK             0x1
8494 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK			0x1
8496 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK			0x1
8498 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK			0x1
8500 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK			0x1
8502 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK			0x1
8504 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK			0x1
8507 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
8508 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		0
8509 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
8511 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
8513 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
8515 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
8517 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK		0x1
8519 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
8521 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK		0x1
8548 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8549 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8550 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8552 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8554 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8556 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8559 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8560 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	0
8561 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK		0x3
8563 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK		0x3
8565 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK		0x3
8568 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8569 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8570 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8572 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8574 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK	0x1
8576 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK	0x1
8578 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK	0x1
8580 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK	0x1
8582 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8585 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8586 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	0
8587 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8589 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8591 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8593 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK	0x1
8595 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK	0x1
8597 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK	0x1
8599 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK	0x1
8617 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8618 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8619 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8621 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8623 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8625 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8628 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
8629 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	0
8630 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK	0x3
8632 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK	0x3
8634 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK	0x3
8637 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8638 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8639 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8641 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8643 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK	0x1
8645 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK	0x1
8647 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK	0x1
8649 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK	0x1
8651 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8654 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8655 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	0
8656 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8658 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8660 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8662 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK	0x1
8664 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK	0x1
8666 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK	0x1
8668 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK	0x1
8686 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8687 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8688 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK		0x1
8690 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK		0x1
8692 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8694 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK		0x1
8696 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK		0x1
8698 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK		0x1
8700 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK		0x1
8703 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK		0x1
8704 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT		0
8705 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK		0x1
8707 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK		0x1
8709 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK		0x1
8711 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK		0x1
8713 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK		0x1
8715 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK		0x1
8717 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
8720 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8721 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	0
8722 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8724 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8726 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8729 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK		0x3
8730 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	0
8731 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK		0x3
8733 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK	0x3
8735 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
8738 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK        0x3
8739 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT       0
8740 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK     0x3
8742 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK	0x3
8744 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK	0x3
8747 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK		0x3
8748 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT		0
8749 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK		0x3
8751 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK	0x3
8753 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK		0x3
8756 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK	0x3
8757 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT	0
8758 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK	0x3
8760 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK	0x3
8762 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK	0x3
8765 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK	0x3
8766 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT	0
8767 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK	0x3
8769 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK	0x3
8771 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8773 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8776 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK		0x1
8777 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT		0
8778 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK		0x1
8780 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK	0x1
8782 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
8784 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK	0x1
8786 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
8788 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK     0x1
8790 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK  0x1
8793 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK		0x1
8794 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT		0
8795 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK		0x1
8797 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK		0x1
8799 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK		0x1
8801 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK	0x1
8803 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK		0x1
8805 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK		0x1
8807 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK		0x1
8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK		0x1
8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT		0
8812 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK		0x1
8814 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK		0x1
8816 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK		0x1
8818 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
8820 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK		0x1
8822 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK		0x1
8824 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
8827 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK		0x1
8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT		0
8829 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
8831 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
8833 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
8835 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK		0x1
8837 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK	0x1
8839 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
8841 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK		0x1
8844 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK		0x1
8845 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT		0
8846 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK		0x1
8848 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
8850 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
8852 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK	0x1
8854 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK		0x1
8856 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK	0x1
8858 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK	0x1
8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK		0x1
8862 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT		0
8863 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK		0x1
8865 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
8867 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
8869 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
8871 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
8873 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
8875 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK	0x1
8879 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT	0
8880 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK		0x1
8882 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK	0x3
8884 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK		0x1
8886 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
8888 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK		0x3
8915 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8916 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8917 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK		0x1
8919 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK		0x1
8921 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8923 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK		0x1
8925 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK		0x1
8927 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK		0x1
8929 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK		0x1
8932 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK		0x1
8933 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT		0
8934 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK		0x1
8936 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK		0x1
8938 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK		0x1
8940 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK		0x1
8942 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK		0x1
8944 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK	0x1
8946 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
8949 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8950 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	0
8951 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8953 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8955 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
8958 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK		0x3
8959 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT		0
8960 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK	0x3
8962 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK	0x3
8964 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
8967 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK	0x3
8968 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT	0
8969 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK	0x3
8971 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK	0x3
8973 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK	0x3
8976 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK	0x3
8977 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT	0
8978 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK	0x3
8980 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK	0x3
8982 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK	0x3
8985 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK	0x3
8986 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT	0
8987 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK	0x3
8989 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK	0x3
8991 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK	0x3
8994 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK	0x3
8995 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT	0
8996 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK	0x3
8998 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9000 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
9002 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
9005 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK		0x1
9006 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT		0
9007 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
9009 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK	0x1
9011 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
9013 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK	0x1
9015 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
9017 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK		0x1
9019 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK		0x1
9022 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK	0x1
9023 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT	0
9024 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK	0x1
9026 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK	0x1
9028 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK	0x1
9030 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK	0x1
9032 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK	0x1
9034 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK	0x1
9036 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK	0x1
9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK		0x1
9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT		0
9041 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK		0x1
9043 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK		0x1
9045 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK		0x1
9047 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
9049 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK		0x1
9051 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK		0x1
9053 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
9056 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		0
9058 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
9060 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
9062 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
9064 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK		0x1
9066 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
9068 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9070 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK		0x1
9073 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK	0x1
9074 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT	0
9075 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK		0x1
9077 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
9079 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
9081 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK		0x1
9083 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK		0x1
9085 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK		0x1
9087 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK		0x1
9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK		0x1
9091 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT		0
9092 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK		0x1
9094 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
9096 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
9098 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
9100 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
9102 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
9104 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK	0x1
9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT	0
9109 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK	0x1
9111 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK	0x1
9113 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK	0x1
9115 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK	0x1
9117 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK	0x1
9119 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK	0x3
9146 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
9147 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
9148 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
9150 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
9152 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
9154 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
9157 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
9158 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
9159 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
9161 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
9163 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
9165 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
9167 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
9169 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
9171 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
9190 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
9191 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
9192 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
9194 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
9196 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
9198 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
9201 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
9202 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
9203 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
9205 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
9207 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
9209 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
9211 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
9213 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
9215 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
9234 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
9235 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
9236 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
9238 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
9240 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
9242 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
9245 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
9246 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
9247 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
9249 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
9251 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
9253 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
9255 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
9257 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
9259 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
9301 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9302 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9303 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
9305 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK	0x1
9307 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
9309 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9311 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK	0x1
9313 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK		0x1
9315 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK		0x1
9318 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK				0x1
9319 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT				0
9320 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK				0x1
9322 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK				0x1
9324 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK				0x1
9326 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK				0x1
9328 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK				0x1
9330 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK				0x1
9332 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK	0x1
9335 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK			0x3
9336 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT			0
9337 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
9339 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
9341 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9344 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK	0x3
9345 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT	0
9346 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9348 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9350 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9353 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9354 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	0
9355 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK	0x3
9357 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK	0x3
9359 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK	0x3
9362 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK		0x3
9363 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT		0
9364 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK		0x3
9366 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK	0x3
9368 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK		0x3
9371 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK	0x3
9372 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9373 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK				0x3
9375 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK				0x3
9377 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK			0x3
9380 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
9381 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
9382 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK	0x3
9384 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9386 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
9388 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
9391 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
9392 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			0
9393 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
9395 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK			0x1
9397 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK			0x1
9399 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
9401 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK			0x1
9403 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK			0x1
9405 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK			0x1
9408 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK				0x1
9409 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT			0
9410 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK				0x1
9412 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK				0x1
9414 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK				0x1
9416 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK			0x1
9418 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK				0x1
9420 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9422 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK				0x1
9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK			0x1
9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT		0
9427 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK		0x1
9429 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
9431 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK		0x1
9433 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
9435 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK               0x1
9437 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
9439 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK	0x1
9442 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
9444 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
9446 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK	0x1
9448 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
9450 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
9452 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
9454 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9456 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK	0x1
9459 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK	0x1
9460 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT	0
9461 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK		0x1
9463 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
9465 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
9467 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK	0x1
9469 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK		0x1
9471 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK		0x1
9473 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK		0x1
9476 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK	0x1
9477 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT	0
9478 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK	0x1
9480 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK	0x1
9482 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK		0x1
9484 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
9486 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK	0x1
9488 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
9490 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
9493 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK		0x1
9494 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT		0
9495 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK		0x1
9497 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK		0x1
9499 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK	0x1
9501 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
9503 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
9505 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK	0x3
9558 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9559 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9560 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
9562 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK		0x1
9564 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK  0x1
9566 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9568 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK	0x1
9570 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
9573 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK		0x3
9574 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT		0
9575 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK		0x3
9577 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9579 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK			0x3
9582 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9583 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	0
9584 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9586 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9588 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9591 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9592 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9593 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK	0x3
9595 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK				0x1
9597 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK			0x1
9599 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK		0x1
9601 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
9604 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK				0x1
9605 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT				0
9606 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK				0x1
9608 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK				0x1
9610 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK				0x1
9612 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK				0x1
9614 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9616 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK	0x1
9618 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK			0x1
9621 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
9622 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		0
9623 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
9625 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK		0x1
9627 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
9629 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK		0x1
9631 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK	0x1
9633 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK		0x1
9635 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK		0x1
9694 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK	0x1
9695 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	0
9696 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
9698 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9700 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9702 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9704 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK		0x1
9706 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK	0x1
9708 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK		0x1
9822 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9823 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		0
9824 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9826 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9828 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK		0x1
9830 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK	0x1
9832 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK	0x1
9834 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK		0x3FF
9872 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK	0x7
9873 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT	0
9874 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK		0x1F
9901 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK	0x1
9902 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT	0
9903 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK	0x7FFFFFFF
9949 	MPA_RTR_TYPE_NONE = 0,
9965 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK	0x1
9966 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT	0
9967 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK		0x1
9969 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK			0x3F
9978 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
9979 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
9980 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK			0x1
9982 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK	0x3
9984 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
9986 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
9989 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK	0x1
9990 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT	0
9991 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
9993 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
9995 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
9997 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
9999 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
10001 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK		0x1
10003 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
10015 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10016 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10017 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
10019 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
10021 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK		0x3
10023 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK		0x3
10026 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK		0x3
10027 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT		0
10028 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
10030 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
10032 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK		0x3
10035 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK			0x1
10036 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT			0
10037 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
10039 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
10041 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK			0x1
10043 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK	0x1
10045 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
10047 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
10049 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
10052 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK		0x1
10053 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT		0
10054 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
10056 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
10058 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
10060 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
10062 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
10064 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
10066 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK	0x1
10084 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK	0x1
10085 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT	0
10086 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK	0x1
10088 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK	0x3
10090 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK	0x3
10092 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK	0x3
10095 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
10096 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		0
10097 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
10099 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK		0x1
10101 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK	0x1
10103 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK	0x1
10105 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
10107 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
10109 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
10140 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
10141 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	0
10142 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
10144 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK			0x3F
10150 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK	0x1
10151 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT	0
10152 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK	0x1
10154 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK		0x3F
10162 #define FCOE_VLAN_FIELDS_VID_MASK	0xFFF
10163 #define FCOE_VLAN_FIELDS_VID_SHIFT	0
10164 #define FCOE_VLAN_FIELDS_CLI_MASK	0x1
10166 #define FCOE_VLAN_FIELDS_PRI_MASK	0x7
10216 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK			0x1
10217 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT		0
10218 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK		0x1
10220 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
10222 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK		0x1
10224 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK		0x1
10226 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK			0x7
10245 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK		0x1
10246 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT		0
10247 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
10249 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK	0x1
10251 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK		0x3
10253 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK			0x7
10280 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK		0x1
10281 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT		0
10282 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
10284 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
10286 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK		0x1
10288 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK			0xF
10290 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK	0xFF
10304 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10305 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10306 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK	0x1
10308 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK	0x1
10310 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
10312 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK	0x1
10314 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK	0x1
10316 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK	0x1
10318 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK	0x1
10321 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK	0x1
10322 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT	0
10323 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK	0x1
10325 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK	0x1
10327 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK		0x1
10329 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK		0x1
10331 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK		0x1
10333 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK		0x1
10335 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK		0x1
10338 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10339 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	0
10340 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10342 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10344 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10347 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10348 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	0
10349 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10351 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10353 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10356 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10357 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	0
10358 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK	0x3
10360 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK	0x3
10362 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK	0x3
10365 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK	0x3
10366 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT	0
10367 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK	0x3
10369 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK	0x3
10371 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK	0x3
10374 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK	0x3
10375 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT	0
10376 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK	0x3
10378 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK	0x3
10380 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK	0x3
10383 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
10384 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
10385 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK	0x3
10387 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
10389 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10391 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10394 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK	0x1
10395 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT	0
10396 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK	0x1
10398 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK	0x1
10400 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK	0x1
10402 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK	0x1
10404 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK	0x1
10406 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK	0x1
10408 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK	0x1
10411 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK	0x1
10412 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT	0
10413 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK	0x1
10415 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK	0x1
10417 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK	0x1
10419 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK	0x1
10421 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK	0x1
10423 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK	0x1
10425 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK	0x1
10428 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK		0x1
10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT		0
10430 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK	0x1
10432 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
10434 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK	0x1
10436 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
10438 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK		0x1
10440 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK	0x1
10442 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK	0x1
10445 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK		0x1
10446 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT		0
10447 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK		0x1
10449 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK		0x1
10451 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK			0x1
10453 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK			0x1
10455 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK			0x1
10457 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
10459 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK	0x1
10462 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK	0x1
10463 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT	0
10464 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK	0x1
10466 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
10468 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
10470 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK	0x1
10472 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK	0x1
10474 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK	0x1
10476 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK	0x1
10479 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK	0x1
10480 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT	0
10481 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK		0x1
10483 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
10485 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
10487 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
10489 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
10491 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
10493 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
10496 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK	0x1
10497 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT	0
10498 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK	0x1
10500 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK	0x1
10502 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK	0x1
10504 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK	0x1
10506 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK	0x1
10508 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK	0x3
10551 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10552 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10553 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK		0x1
10555 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK		0x1
10557 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK		0x1
10559 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK		0x1
10561 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK		0x1
10563 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK	0x3
10566 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
10567 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		0
10568 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK			0x3
10570 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK	0x3
10572 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK			0x3
10575 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10576 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	0
10577 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10579 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10581 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10584 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK			0x3
10585 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT			0
10586 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK			0x3
10588 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK	0x1
10590 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
10592 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK			0x1
10594 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
10597 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10598 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		0
10599 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10601 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10603 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK		0x1
10605 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK		0x1
10607 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK		0x1
10609 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK		0x1
10611 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10614 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10615 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10616 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10618 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10620 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10622 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10624 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10626 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10628 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10638 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10639 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10640 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10642 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10644 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10646 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10649 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10650 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	0
10651 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10653 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10655 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10658 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10659 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10660 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10662 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10664 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK		0x1
10666 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10668 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10670 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10672 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10675 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10676 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10677 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10679 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10681 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10683 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10685 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10687 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10689 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10709 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK	0x1
10710 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT	0
10711 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK	0x1
10713 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK		0x3F
10721 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK	0x3
10722 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT	0
10723 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK	0x3F
10735 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10736 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10737 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10739 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10741 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10743 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10746 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10747 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10748 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10750 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10752 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10754 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10756 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10758 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10760 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10774 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1
10775 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10776 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1
10778 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
10876 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10877 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10878 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10880 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10882 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10884 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10887 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10888 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10889 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10891 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10893 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10895 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10897 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10899 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10901 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10937 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10938 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10939 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
10941 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK	0x1
10943 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
10945 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
10947 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK	0x1
10949 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK		0x1
10951 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK		0x1
10954 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK		0x1
10955 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT		0
10956 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK		0x1
10958 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK		0x1
10960 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK		0x1
10962 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK		0x1
10964 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK		0x1
10966 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK		0x1
10968 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK	0x1
10971 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK			0x3
10972 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT			0
10973 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK			0x3
10975 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK			0x3
10977 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
10980 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
10981 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	0
10982 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
10984 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
10986 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
10989 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
10990 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	0
10991 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK	0x3
10993 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK	0x3
10995 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK	0x3
10998 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK				0x3
10999 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT				0
11000 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK				0x3
11002 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK				0x3
11004 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK	0x3
11007 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK		0x3
11008 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT		0
11009 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK		0x3
11011 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK		0x3
11013 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK	0x3
11016 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK	0x3
11017 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT	0
11018 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK	0x3
11020 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK		0x3
11022 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
11024 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK			0x1
11027 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK			0x1
11028 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT			0
11029 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
11031 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK			0x1
11033 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK			0x1
11035 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK			0x1
11037 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK			0x1
11039 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK			0x1
11041 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK			0x1
11044 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK				0x1
11045 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT			0
11046 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK				0x1
11048 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK				0x1
11050 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK				0x1
11052 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK				0x1
11054 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK	0x1
11056 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK				0x1
11058 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK				0x1
11061 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK				0x1
11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT			0
11063 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK			0x1
11065 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK		0x1
11067 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK		0x1
11069 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
11071 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK		0x1
11073 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK			0x1
11075 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK	0x1
11078 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
11079 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
11080 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11082 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK	0x1
11084 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11086 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11088 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11090 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
11092 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK	0x1
11095 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK		0x1
11096 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT	0
11097 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK		0x1
11099 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
11101 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
11103 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK		0x1
11105 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK		0x1
11107 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK		0x1
11109 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK		0x1
11112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK	0x1
11113 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT	0
11114 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK		0x1
11116 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
11118 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
11120 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
11122 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
11124 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
11126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
11129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK			0x1
11130 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT			0
11131 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK			0x1
11133 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK			0x1
11135 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK			0x1
11137 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK			0x1
11139 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK	0x1
11141 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK	0x3
11194 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
11195 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
11196 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK		0x1
11198 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK		0x1
11200 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK		0x1
11202 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
11204 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK		0x1
11206 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK		0x3
11209 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK		0x3
11210 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT		0
11211 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK		0x3
11213 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
11215 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK			0x3
11218 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11219 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	0
11220 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11222 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
11224 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
11227 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
11228 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT		0
11229 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK	0x3
11231 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
11233 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK	0x1
11235 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK	0x1
11237 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
11240 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
11241 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		0
11242 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
11244 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
11246 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK		0x1
11248 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK		0x1
11250 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
11252 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK	0x1
11254 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11257 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11258 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
11259 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11261 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11263 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11265 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11267 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11269 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11271 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
11291 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11292 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11293 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11295 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11297 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11299 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11302 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK	0x3
11303 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT	0
11304 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
11306 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11308 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11311 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11312 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11313 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11315 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11317 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK		0x1
11319 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
11321 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
11323 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
11325 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11328 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11329 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
11330 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11332 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11334 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11336 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11338 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11340 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11342 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
11365 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11366 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11367 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11369 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11371 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11373 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11376 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11377 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11378 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11380 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11382 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11384 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11386 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11388 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11390 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11440 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11441 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11442 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11444 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11446 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11448 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11451 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11452 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11453 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11455 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11457 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11459 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11461 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11463 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11465 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11480 #define MFW_TRACE_SIGNATURE     0x25071946
11483 #define MFW_TRACE_EVENTID_MASK          0x00ffff
11484 #define MFW_TRACE_PRM_SIZE_MASK         0x0f0000
11493 				 * 0 - just errors will be written to the buffer
11495 	u32 modules_mask[2];	/* a bit per module, 1 means write it, 0 means
11517 #define OFFSIZE_OFFSET_SHIFT	0
11518 #define OFFSIZE_OFFSET_MASK	0x0000ffff
11521 #define OFFSIZE_SIZE_MASK	0xffff0000
11541 #define ETH_SPEED_AUTONEG			0x0
11542 #define ETH_SPEED_SMARTLINQ			0x8
11545 #define ETH_PAUSE_NONE				0x0
11546 #define ETH_PAUSE_AUTONEG			0x1
11547 #define ETH_PAUSE_RX				0x2
11548 #define ETH_PAUSE_TX				0x4
11553 #define ETH_LOOPBACK_NONE			0x0
11554 #define ETH_LOOPBACK_INT_PHY			0x1
11555 #define ETH_LOOPBACK_EXT_PHY			0x2
11556 #define ETH_LOOPBACK_EXT			0x3
11557 #define ETH_LOOPBACK_MAC			0x4
11558 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123		0x5
11559 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301		0x6
11560 #define ETH_LOOPBACK_PCS_AH_ONLY		0x7
11561 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY	0x8
11562 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY	0x9
11565 #define EEE_CFG_EEE_ENABLED			BIT(0)
11569 #define EEE_TX_TIMER_USEC_MASK			0xfffffff0
11571 #define EEE_TX_TIMER_USEC_BALANCED_TIME		0xa00
11572 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	0x100
11573 #define EEE_TX_TIMER_USEC_LATENCY_TIME		0x6000
11578 #define FEC_FORCE_MODE_MASK			0x000000ff
11579 #define FEC_FORCE_MODE_OFFSET			0
11580 #define FEC_FORCE_MODE_NONE			0x00
11581 #define FEC_FORCE_MODE_FIRECODE			0x01
11582 #define FEC_FORCE_MODE_RS			0x02
11583 #define FEC_FORCE_MODE_AUTO			0x07
11584 #define FEC_EXTENDED_MODE_MASK			0xffffff00
11586 #define ETH_EXT_FEC_NONE			0x00000100
11587 #define ETH_EXT_FEC_10G_NONE			0x00000200
11588 #define ETH_EXT_FEC_10G_BASE_R			0x00000400
11589 #define ETH_EXT_FEC_20G_NONE			0x00000800
11590 #define ETH_EXT_FEC_20G_BASE_R			0x00001000
11591 #define ETH_EXT_FEC_25G_NONE			0x00002000
11592 #define ETH_EXT_FEC_25G_BASE_R			0x00004000
11593 #define ETH_EXT_FEC_25G_RS528			0x00008000
11594 #define ETH_EXT_FEC_40G_NONE			0x00010000
11595 #define ETH_EXT_FEC_40G_BASE_R			0x00020000
11596 #define ETH_EXT_FEC_50G_NONE			0x00040000
11597 #define ETH_EXT_FEC_50G_BASE_R			0x00080000
11598 #define ETH_EXT_FEC_50G_RS528			0x00100000
11599 #define ETH_EXT_FEC_50G_RS544			0x00200000
11600 #define ETH_EXT_FEC_100G_NONE			0x00400000
11601 #define ETH_EXT_FEC_100G_BASE_R			0x00800000
11602 #define ETH_EXT_FEC_100G_RS528			0x01000000
11603 #define ETH_EXT_FEC_100G_RS544			0x02000000
11606 #define ETH_EXT_SPEED_MASK			0x0000ffff
11607 #define ETH_EXT_SPEED_OFFSET			0
11608 #define ETH_EXT_SPEED_AN			0x00000001
11609 #define ETH_EXT_SPEED_1G			0x00000002
11610 #define ETH_EXT_SPEED_10G			0x00000004
11611 #define ETH_EXT_SPEED_20G			0x00000008
11612 #define ETH_EXT_SPEED_25G			0x00000010
11613 #define ETH_EXT_SPEED_40G			0x00000020
11614 #define ETH_EXT_SPEED_50G_BASE_R		0x00000040
11615 #define ETH_EXT_SPEED_50G_BASE_R2		0x00000080
11616 #define ETH_EXT_SPEED_100G_BASE_R2		0x00000100
11617 #define ETH_EXT_SPEED_100G_BASE_R4		0x00000200
11618 #define ETH_EXT_SPEED_100G_BASE_P4		0x00000400
11619 #define ETH_EXT_ADV_SPEED_MASK			0xffff0000
11621 #define ETH_EXT_ADV_SPEED_RESERVED		0x00010000
11622 #define ETH_EXT_ADV_SPEED_1G			0x00020000
11623 #define ETH_EXT_ADV_SPEED_10G			0x00040000
11624 #define ETH_EXT_ADV_SPEED_20G			0x00080000
11625 #define ETH_EXT_ADV_SPEED_25G			0x00100000
11626 #define ETH_EXT_ADV_SPEED_40G			0x00200000
11627 #define ETH_EXT_ADV_SPEED_50G_BASE_R		0x00400000
11628 #define ETH_EXT_ADV_SPEED_50G_BASE_R2		0x00800000
11629 #define ETH_EXT_ADV_SPEED_100G_BASE_R2		0x01000000
11630 #define ETH_EXT_ADV_SPEED_100G_BASE_R4		0x02000000
11631 #define ETH_EXT_ADV_SPEED_100G_BASE_P4		0x04000000
11636 #define PORT_MF_CFG_OV_TAG_MASK		0x0000ffff
11637 #define PORT_MF_CFG_OV_TAG_SHIFT	0
11738 #define PORT_CMT_IN_TEAM	(1 << 0)
11741 #define PORT_CMT_PORT_INACTIVE	(0 << 1)
11745 #define PORT_CMT_TEAM0		(0 << 2)
11755 	LLDP_NEAREST_BRIDGE = 0,
11763 #define LLDP_CONFIG_TX_INTERVAL_MASK	0x000000ff
11764 #define LLDP_CONFIG_TX_INTERVAL_SHIFT	0
11765 #define LLDP_CONFIG_HOLD_MASK		0x00000f00
11767 #define LLDP_CONFIG_MAX_CREDIT_MASK	0x0000f000
11769 #define LLDP_CONFIG_ENABLE_RX_MASK	0x40000000
11771 #define LLDP_CONFIG_ENABLE_TX_MASK	0x80000000
11787 #define DCBX_ETS_ENABLED_MASK	0x00000001
11788 #define DCBX_ETS_ENABLED_SHIFT	0
11789 #define DCBX_ETS_WILLING_MASK	0x00000002
11791 #define DCBX_ETS_ERROR_MASK	0x00000004
11793 #define DCBX_ETS_CBS_MASK	0x00000008
11795 #define DCBX_ETS_MAX_TCS_MASK	0x000000f0
11797 #define DCBX_OOO_TC_MASK	0x00000f00
11803 #define DCBX_CEE_STRICT_PRIORITY	0xf
11806 #define DCBX_ETS_TSA_STRICT	0
11816 #define DCBX_APP_PRI_MAP_MASK		0x000000ff
11817 #define DCBX_APP_PRI_MAP_SHIFT		0
11818 #define DCBX_APP_PRI_0			0x01
11819 #define DCBX_APP_PRI_1			0x02
11820 #define DCBX_APP_PRI_2			0x04
11821 #define DCBX_APP_PRI_3			0x08
11822 #define DCBX_APP_PRI_4			0x10
11823 #define DCBX_APP_PRI_5			0x20
11824 #define DCBX_APP_PRI_6			0x40
11825 #define DCBX_APP_PRI_7			0x80
11826 #define DCBX_APP_SF_MASK		0x00000300
11828 #define DCBX_APP_SF_ETHTYPE		0
11830 #define DCBX_APP_SF_IEEE_MASK		0x0000f000
11832 #define DCBX_APP_SF_IEEE_RESERVED	0
11838 #define DCBX_APP_PROTOCOL_ID_MASK	0xffff0000
11844 #define DCBX_APP_ENABLED_MASK		0x00000001
11845 #define DCBX_APP_ENABLED_SHIFT		0
11846 #define DCBX_APP_WILLING_MASK		0x00000002
11848 #define DCBX_APP_ERROR_MASK		0x00000004
11850 #define DCBX_APP_MAX_TCS_MASK		0x0000f000
11852 #define DCBX_APP_NUM_ENTRIES_MASK	0x00ff0000
11860 #define DCBX_PFC_PRI_EN_BITMAP_MASK	0x000000ff
11861 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT	0
11862 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0	0x01
11863 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1	0x02
11864 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2	0x04
11865 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3	0x08
11866 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4	0x10
11867 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5	0x20
11868 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6	0x40
11869 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7	0x80
11871 #define DCBX_PFC_FLAGS_MASK		0x0000ff00
11873 #define DCBX_PFC_CAPS_MASK		0x00000f00
11875 #define DCBX_PFC_MBC_MASK		0x00004000
11877 #define DCBX_PFC_WILLING_MASK		0x00008000
11879 #define DCBX_PFC_ENABLED_MASK		0x00010000
11881 #define DCBX_PFC_ERROR_MASK		0x00020000
11889 #define DCBX_CONFIG_VERSION_MASK	0x00000007
11890 #define DCBX_CONFIG_VERSION_SHIFT	0
11891 #define DCBX_CONFIG_VERSION_DISABLED	0
11915 #define DCB_DSCP_ENABLE_MASK	0x1
11916 #define DCB_DSCP_ENABLE_SHIFT	0
11952 #define PROCESS_KILL_COUNTER_MASK	0x0000ffff
11953 #define PROCESS_KILL_COUNTER_SHIFT	0
11954 #define PROCESS_KILL_GLOB_AEU_BIT_MASK	0xffff0000
11963 #define LINK_STATUS_LINK_UP				0x00000001
11964 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001e
11973 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
11974 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
11975 #define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
11976 #define LINK_STATUS_PFC_ENABLED				0x00000100
11977 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
11978 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
11979 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE		0x00000800
11980 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE		0x00001000
11981 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE		0x00002000
11982 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE		0x00004000
11983 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE		0x00008000
11984 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE		0x00010000
11985 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000c0000
11986 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0 << 18)
11990 #define LINK_STATUS_SFP_TX_FAULT			0x00100000
11991 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00200000
11992 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00400000
11993 #define LINK_STATUS_RX_SIGNAL_PRESENT			0x00800000
11994 #define LINK_STATUS_MAC_LOCAL_FAULT			0x01000000
11995 #define LINK_STATUS_MAC_REMOTE_FAULT			0x02000000
11996 #define LINK_STATUS_UNSUPPORTED_SPD_REQ			0x04000000
11998 #define LINK_STATUS_FEC_MODE_MASK			0x38000000
11999 #define LINK_STATUS_FEC_MODE_NONE			(0 << 27)
12015 #define MEDIA_UNSPECIFIED	0x0
12016 #define MEDIA_SFPP_10G_FIBER	0x1
12017 #define MEDIA_XFP_FIBER		0x2
12018 #define MEDIA_DA_TWINAX		0x3
12019 #define MEDIA_BASE_T		0x4
12020 #define MEDIA_SFP_1G_FIBER	0x5
12021 #define MEDIA_MODULE_FIBER	0x6
12022 #define MEDIA_KR		0xf0
12023 #define MEDIA_NOT_PRESENT	0xff
12040 #define ETH_TRANSCEIVER_STATE_MASK			0x000000ff
12041 #define ETH_TRANSCEIVER_STATE_SHIFT			0x00000000
12042 #define ETH_TRANSCEIVER_STATE_OFFSET			0x00000000
12043 #define ETH_TRANSCEIVER_STATE_UNPLUGGED			0x00000000
12044 #define ETH_TRANSCEIVER_STATE_PRESENT			0x00000001
12045 #define ETH_TRANSCEIVER_STATE_VALID			0x00000003
12046 #define ETH_TRANSCEIVER_STATE_UPDATING			0x00000008
12047 #define ETH_TRANSCEIVER_TYPE_MASK			0x0000ff00
12048 #define ETH_TRANSCEIVER_TYPE_OFFSET			0x8
12049 #define ETH_TRANSCEIVER_TYPE_NONE			0x00
12050 #define ETH_TRANSCEIVER_TYPE_UNKNOWN			0xff
12051 #define ETH_TRANSCEIVER_TYPE_1G_PCC			0x01
12052 #define ETH_TRANSCEIVER_TYPE_1G_ACC			0x02
12053 #define ETH_TRANSCEIVER_TYPE_1G_LX			0x03
12054 #define ETH_TRANSCEIVER_TYPE_1G_SX			0x04
12055 #define ETH_TRANSCEIVER_TYPE_10G_SR			0x05
12056 #define ETH_TRANSCEIVER_TYPE_10G_LR			0x06
12057 #define ETH_TRANSCEIVER_TYPE_10G_LRM			0x07
12058 #define ETH_TRANSCEIVER_TYPE_10G_ER			0x08
12059 #define ETH_TRANSCEIVER_TYPE_10G_PCC			0x09
12060 #define ETH_TRANSCEIVER_TYPE_10G_ACC			0x0a
12061 #define ETH_TRANSCEIVER_TYPE_XLPPI			0x0b
12062 #define ETH_TRANSCEIVER_TYPE_40G_LR4			0x0c
12063 #define ETH_TRANSCEIVER_TYPE_40G_SR4			0x0d
12064 #define ETH_TRANSCEIVER_TYPE_40G_CR4			0x0e
12065 #define ETH_TRANSCEIVER_TYPE_100G_AOC			0x0f
12066 #define ETH_TRANSCEIVER_TYPE_100G_SR4			0x10
12067 #define ETH_TRANSCEIVER_TYPE_100G_LR4			0x11
12068 #define ETH_TRANSCEIVER_TYPE_100G_ER4			0x12
12069 #define ETH_TRANSCEIVER_TYPE_100G_ACC			0x13
12070 #define ETH_TRANSCEIVER_TYPE_100G_CR4			0x14
12071 #define ETH_TRANSCEIVER_TYPE_4x10G_SR			0x15
12072 #define ETH_TRANSCEIVER_TYPE_25G_CA_N			0x16
12073 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S			0x17
12074 #define ETH_TRANSCEIVER_TYPE_25G_CA_S			0x18
12075 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M			0x19
12076 #define ETH_TRANSCEIVER_TYPE_25G_CA_L			0x1a
12077 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L			0x1b
12078 #define ETH_TRANSCEIVER_TYPE_25G_SR			0x1c
12079 #define ETH_TRANSCEIVER_TYPE_25G_LR			0x1d
12080 #define ETH_TRANSCEIVER_TYPE_25G_AOC			0x1e
12081 #define ETH_TRANSCEIVER_TYPE_4x10G			0x1f
12082 #define ETH_TRANSCEIVER_TYPE_4x25G_CR			0x20
12083 #define ETH_TRANSCEIVER_TYPE_1000BASET			0x21
12084 #define ETH_TRANSCEIVER_TYPE_10G_BASET			0x22
12085 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR	0x30
12086 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR	0x31
12087 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR	0x32
12088 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR	0x33
12089 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR	0x34
12090 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR	0x35
12091 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC	0x36
12092 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR	0x37
12093 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR	0x38
12094 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR	0x39
12095 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR	0x3a
12103 #define EEE_ACTIVE_BIT			BIT(0)
12104 #define EEE_LD_ADV_STATUS_MASK		0x000000f0
12108 #define EEE_LP_ADV_STATUS_MASK		0x00000f00
12110 #define EEE_SUPPORTED_SPEED_MASK	0x0000f000
12116 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
12117 #define EEE_REMOTE_TW_TX_OFFSET 0
12118 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
12123 #define OEM_CFG_CHANNEL_TYPE_MASK                       0x00000003
12124 #define OEM_CFG_CHANNEL_TYPE_OFFSET                     0
12125 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION             0x1
12126 #define OEM_CFG_CHANNEL_TYPE_STAGGED                    0x2
12127 #define OEM_CFG_SCHED_TYPE_MASK                         0x0000000C
12129 #define OEM_CFG_SCHED_TYPE_ETS                          0x1
12130 #define OEM_CFG_SCHED_TYPE_VNIC_BW                      0x2
12141 #define FUNC_MF_CFG_FUNC_HIDE			0x00000001
12142 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING		0x00000002
12143 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT	0x00000001
12145 #define FUNC_MF_CFG_PROTOCOL_MASK	0x000000f0
12147 #define FUNC_MF_CFG_PROTOCOL_ETHERNET	0x00000000
12148 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
12149 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
12150 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
12151 #define FUNC_MF_CFG_PROTOCOL_NVMETCP    0x00000040
12152 #define FUNC_MF_CFG_PROTOCOL_MAX	0x00000040
12154 #define FUNC_MF_CFG_MIN_BW_MASK		0x0000ff00
12156 #define FUNC_MF_CFG_MIN_BW_DEFAULT	0x00000000
12157 #define FUNC_MF_CFG_MAX_BW_MASK		0x00ff0000
12159 #define FUNC_MF_CFG_MAX_BW_DEFAULT	0x00640000
12162 #define FUNC_STATUS_VIRTUAL_LINK_UP	0x00000001
12165 #define FUNC_MF_CFG_UPPERMAC_MASK	0x0000ffff
12166 #define FUNC_MF_CFG_UPPERMAC_SHIFT	0
12169 #define FUNC_MF_CFG_LOWERMAC_DEFAULT	0xffffffff
12178 #define FUNC_MF_CFG_OV_STAG_MASK	0x0000ffff
12179 #define FUNC_MF_CFG_OV_STAG_SHIFT	0
12191 #define DRV_ID_PDA_COMP_VER_MASK	0x0000ffff
12192 #define DRV_ID_PDA_COMP_VER_SHIFT	0
12195 #define DRV_ID_MCP_HSI_VER_MASK		0x00ff0000
12200 #define DRV_ID_DRV_TYPE_MASK		0x7f000000
12202 #define DRV_ID_DRV_TYPE_UNKNOWN		(0 << DRV_ID_DRV_TYPE_SHIFT)
12205 #define DRV_ID_DRV_INIT_HW_MASK		0x80000000
12210 #define OEM_CFG_FUNC_TC_MASK                    0x0000000F
12211 #define OEM_CFG_FUNC_TC_OFFSET                  0
12212 #define OEM_CFG_FUNC_TC_0                       0x0
12213 #define OEM_CFG_FUNC_TC_1                       0x1
12214 #define OEM_CFG_FUNC_TC_2                       0x2
12215 #define OEM_CFG_FUNC_TC_3                       0x3
12216 #define OEM_CFG_FUNC_TC_4                       0x4
12217 #define OEM_CFG_FUNC_TC_5                       0x5
12218 #define OEM_CFG_FUNC_TC_6                       0x6
12219 #define OEM_CFG_FUNC_TC_7                       0x7
12221 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK         0x00000030
12223 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC         0x1
12224 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS           0x2
12293 	RESOURCE_NUM_SB_E = 0,
12317 	RESOURCE_NUM_INVALID = 0xFFFFFFFF
12330 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12333 #define DRV_ROLE_NONE           0
12343 #define LOAD_REQ_ROLE_MASK              0x000000FF
12344 #define LOAD_REQ_ROLE_SHIFT             0
12345 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
12347 #define LOAD_REQ_LOCK_TO_DEFAULT        0
12349 #define LOAD_REQ_FORCE_MASK             0x000F0000
12351 #define LOAD_REQ_FORCE_NONE             0
12354 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
12356 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
12364 #define LOAD_RSP_ROLE_MASK              0x000000FF
12365 #define LOAD_RSP_ROLE_SHIFT             0
12366 #define LOAD_RSP_HSI_MASK               0x0000FF00
12368 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
12370 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
12407 #define DRV_MSG_CODE_MASK			0xffff0000
12408 #define DRV_MSG_CODE_LOAD_REQ			0x10000000
12409 #define DRV_MSG_CODE_LOAD_DONE			0x11000000
12410 #define DRV_MSG_CODE_INIT_HW			0x12000000
12411 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
12412 #define DRV_MSG_CODE_UNLOAD_REQ			0x20000000
12413 #define DRV_MSG_CODE_UNLOAD_DONE		0x21000000
12414 #define DRV_MSG_CODE_INIT_PHY			0x22000000
12415 #define DRV_MSG_CODE_LINK_RESET			0x23000000
12416 #define DRV_MSG_CODE_SET_DCBX			0x25000000
12417 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG         0x26000000
12418 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM          0x27000000
12419 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS    0x28000000
12420 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER     0x29000000
12421 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE     0x31000000
12422 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12423 #define DRV_MSG_CODE_OV_UPDATE_MTU              0x33000000
12424 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG		0x34000000
12425 #define DRV_MSG_SET_RESOURCE_VALUE_MSG		0x35000000
12426 #define DRV_MSG_CODE_OV_UPDATE_WOL              0x38000000
12427 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE     0x39000000
12428 #define DRV_MSG_CODE_GET_OEM_UPDATES            0x41000000
12430 #define DRV_MSG_CODE_BW_UPDATE_ACK		0x32000000
12431 #define DRV_MSG_CODE_NIG_DRAIN			0x30000000
12432 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK		0x3b000000
12433 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION		0x003e0000
12434 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION		0x003f0000
12435 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
12436 #define DRV_MSG_CODE_VF_DISABLED_DONE		0xc0000000
12437 #define DRV_MSG_CODE_CFG_VF_MSIX		0xc0010000
12438 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX		0xc0020000
12439 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN		0x00010000
12440 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA		0x00020000
12441 #define DRV_MSG_CODE_NVM_GET_FILE_ATT		0x00030000
12442 #define DRV_MSG_CODE_NVM_READ_NVRAM		0x00050000
12443 #define DRV_MSG_CODE_NVM_WRITE_NVRAM		0x00060000
12444 #define DRV_MSG_CODE_MCP_RESET			0x00090000
12445 #define DRV_MSG_CODE_SET_VERSION		0x000f0000
12446 #define DRV_MSG_CODE_MCP_HALT                   0x00100000
12447 #define DRV_MSG_CODE_SET_VMAC                   0x00110000
12448 #define DRV_MSG_CODE_GET_VMAC                   0x00120000
12450 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
12455 #define DRV_MSG_CODE_GET_STATS                  0x00130000
12461 #define DRV_MSG_CODE_TRANSCEIVER_READ           0x00160000
12463 #define DRV_MSG_CODE_MASK_PARITIES              0x001a0000
12465 #define DRV_MSG_CODE_BIST_TEST			0x001e0000
12466 #define DRV_MSG_CODE_SET_LED_MODE		0x00200000
12467 #define DRV_MSG_CODE_RESOURCE_CMD		0x00230000
12468 /* Send crash dump commands with param[3:0] - opcode */
12469 #define DRV_MSG_CODE_MDUMP_CMD			0x00250000
12470 #define DRV_MSG_CODE_GET_TLV_DONE		0x002f0000
12471 #define DRV_MSG_CODE_GET_ENGINE_CONFIG		0x00370000
12472 #define DRV_MSG_CODE_GET_PPFID_BITMAP		0x43000000
12474 #define DRV_MSG_CODE_DEBUG_DATA_SEND		0xc0040000
12476 #define RESOURCE_CMD_REQ_RESC_MASK		0x0000001F
12477 #define RESOURCE_CMD_REQ_RESC_SHIFT		0
12478 #define RESOURCE_CMD_REQ_OPCODE_MASK		0x000000E0
12485 #define RESOURCE_CMD_REQ_AGE_MASK		0x0000FF00
12488 #define RESOURCE_CMD_RSP_OWNER_MASK		0x000000FF
12489 #define RESOURCE_CMD_RSP_OWNER_SHIFT		0
12490 #define RESOURCE_CMD_RSP_OPCODE_MASK		0x00000700
12499 #define RESOURCE_DUMP				0
12502 #define MDUMP_DRV_PARAM_OPCODE_MASK             0x0000000f
12503 #define DRV_MSG_CODE_MDUMP_ACK                  0x01
12504 #define DRV_MSG_CODE_MDUMP_SET_VALUES           0x02
12505 #define DRV_MSG_CODE_MDUMP_TRIGGER              0x03
12506 #define DRV_MSG_CODE_MDUMP_GET_CONFIG           0x04
12507 #define DRV_MSG_CODE_MDUMP_SET_ENABLE           0x05
12508 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS           0x06
12509 #define DRV_MSG_CODE_MDUMP_GET_RETAIN           0x07
12510 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN           0x08
12512 #define DRV_MSG_CODE_HW_DUMP_TRIGGER            0x0a
12513 #define DRV_MSG_CODE_MDUMP_GEN_MDUMP2           0x0b
12514 #define DRV_MSG_CODE_MDUMP_FREE_MDUMP2          0x0c
12516 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL	0x002b0000
12517 #define DRV_MSG_CODE_OS_WOL			0x002e0000
12519 #define DRV_MSG_CODE_FEATURE_SUPPORT		0x00300000
12520 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT	0x00310000
12521 #define DRV_MSG_SEQ_NUMBER_MASK			0x0000ffff
12524 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
12525 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
12526 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
12527 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
12528 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK		0x000000FF
12531 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI     0x3
12532 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET          0
12533 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
12535 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
12537 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT	0
12538 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK	0x000000FF
12540 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK	0x0000FF00
12541 #define DRV_MB_PARAM_LLDP_SEND_MASK		0x00000001
12542 #define DRV_MB_PARAM_LLDP_SEND_SHIFT		0
12544 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT		0
12545 #define DRV_MB_PARAM_OV_CURR_CFG_MASK		0x0000000F
12546 #define DRV_MB_PARAM_OV_CURR_CFG_NONE		0
12551 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT	0
12552 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK	0xFFFFFFFF
12553 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK	0xFF000000
12554 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK	0x00FF0000
12555 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK	0x0000FF00
12556 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK	0x000000FF
12558 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT	0
12559 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK	0xF
12560 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN	0x1
12561 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED	0x2
12562 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING	0x3
12563 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED	0x4
12564 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE	0x5
12566 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT	0
12567 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK	0xFFFFFFFF
12579 #define DRV_MB_PARAM_ESWITCH_MODE_NONE	0x0
12580 #define DRV_MB_PARAM_ESWITCH_MODE_VEB	0x1
12581 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA	0x2
12583 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK	0x1
12584 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET	0
12586 #define DRV_MB_PARAM_SET_LED_MODE_OPER		0x0
12587 #define DRV_MB_PARAM_SET_LED_MODE_ON		0x1
12588 #define DRV_MB_PARAM_SET_LED_MODE_OFF		0x2
12590 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET			0
12591 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK			0x00000003
12593 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK			0x000000fc
12595 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK		0x0000ff00
12597 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK			0xffff0000
12600 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK		0xffff0000
12602 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK		0x0000ffff
12603 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
12610 #define DRV_MB_PARAM_BIST_RC_UNKNOWN				0
12615 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT			0
12616 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK			0x000000ff
12618 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK			0x0000ff00
12620 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK			0x0000ffff
12621 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET		0
12622 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE			0x00000002
12623 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL		0x00000004
12624 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL	0x00000008
12625 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK			0x00010000
12628 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET		0
12629 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK			0xff
12632 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET			0
12633 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK				0x00ffffff
12635 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK				0xff000000
12637 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET			0
12638 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT			0
12639 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK			0x0000ffff
12641 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK			0x00010000
12643 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK			0x00020000
12645 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK			0x00040000
12647 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK			0x00080000
12649 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK		0x00100000
12651 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK		0x0f000000
12654 #define FW_MSG_CODE_MASK			0xffff0000
12655 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
12656 #define FW_MSG_CODE_DRV_LOAD_ENGINE		0x10100000
12657 #define FW_MSG_CODE_DRV_LOAD_PORT		0x10110000
12658 #define FW_MSG_CODE_DRV_LOAD_FUNCTION		0x10120000
12659 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA	0x10200000
12660 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1	0x10210000
12661 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG	0x10220000
12662 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
12663 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12664 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
12665 #define FW_MSG_CODE_DRV_LOAD_DONE		0x11100000
12666 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE		0x20110000
12667 #define FW_MSG_CODE_DRV_UNLOAD_PORT		0x20120000
12668 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION		0x20130000
12669 #define FW_MSG_CODE_DRV_UNLOAD_DONE		0x21100000
12670 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
12671 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
12672 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
12673 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE	0x3b000000
12674 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE	0xb0010000
12676 #define FW_MSG_CODE_NVM_OK			0x00010000
12677 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK	0x00400000
12678 #define FW_MSG_CODE_PHY_OK			0x00110000
12679 #define FW_MSG_CODE_OK				0x00160000
12680 #define FW_MSG_CODE_ERROR			0x00170000
12681 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK		0x00160000
12682 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR	0x00170000
12683 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT	0x00020000
12685 #define FW_MSG_CODE_OS_WOL_SUPPORTED            0x00800000
12686 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED        0x00810000
12687 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE	0x00870000
12688 #define FW_MSG_SEQ_NUMBER_MASK			0x0000ffff
12690 #define FW_MSG_CODE_DEBUG_DATA_SEND_INV_ARG	0xb0070000
12691 #define FW_MSG_CODE_DEBUG_DATA_SEND_BUF_FULL	0xb0080000
12692 #define FW_MSG_CODE_DEBUG_DATA_SEND_NO_BUF	0xb0090000
12693 #define FW_MSG_CODE_DEBUG_NOT_ENABLED		0xb00a0000
12694 #define FW_MSG_CODE_DEBUG_DATA_SEND_OK		0xb00b0000
12696 #define FW_MSG_CODE_MDUMP_INVALID_CMD		0x00030000
12699 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK		0xffff0000
12701 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK		0x0000ffff
12702 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
12705 #define FW_MB_PARAM_GET_PF_RDMA_NONE				0x0
12706 #define FW_MB_PARAM_GET_PF_RDMA_ROCE				0x1
12707 #define FW_MB_PARAM_GET_PF_RDMA_IWARP				0x2
12708 #define FW_MB_PARAM_GET_PF_RDMA_BOTH				0x3
12711 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ			BIT(0)
12717 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR			BIT(0)
12719 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK		0x00000001
12720 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT		0
12721 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK		0x00000002
12723 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK			0x00000004
12725 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK			0x00000008
12728 #define FW_MB_PARAM_PPFID_BITMAP_MASK				0xff
12729 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT				0
12732 #define DRV_PULSE_SEQ_MASK					0x00007fff
12733 #define DRV_PULSE_SYSTEM_TIME_MASK				0xffff0000
12734 #define DRV_PULSE_ALWAYS_ALIVE					0x00008000
12737 #define MCP_PULSE_SEQ_MASK					0x00007fff
12738 #define MCP_PULSE_ALWAYS_ALIVE					0x00008000
12739 #define MCP_EVENT_MASK						0xffff0000
12740 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ			0x00010000
12745 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK		0x00ffffff
12746 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT		0
12747 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK			0xff000000
12775 #define MFW_DRV_MSG_OFFSET(msg_id)	((msg_id & 0x3) << 3)
12776 #define MFW_DRV_MSG_MASK(msg_id)	(0xff << MFW_DRV_MSG_OFFSET(msg_id))
13036 #define NVM_CFG_MAC_ADDRESS_HI_MASK				0x0000ffff
13037 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET				0
13044 #define NVM_CFG1_GLOB_MF_MODE_MASK				0x00000ff0
13046 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED			0x0
13047 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT				0x1
13048 #define NVM_CFG1_GLOB_MF_MODE_SPIO4				0x2
13049 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0				0x3
13050 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5				0x4
13051 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0				0x5
13052 #define NVM_CFG1_GLOB_MF_MODE_BD				0x6
13053 #define NVM_CFG1_GLOB_MF_MODE_UFP				0x7
13062 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK			0x000000ff
13063 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET			0
13064 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G		0x0
13065 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G			0x1
13066 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G		0x2
13067 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F			0x3
13068 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E		0x4
13069 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G		0x5
13070 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G			0xb
13071 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G			0xc
13072 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G			0xd
13073 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G			0xe
13074 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G			0xf
13075 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1		0x11
13076 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1		0x12
13077 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2		0x13
13078 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2		0x14
13079 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4		0x15
13102 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK			0x000000ff
13103 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET			0
13104 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK			0x0000ff00
13106 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK			0x00ff0000
13113 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET		0x1
13114 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE			0x2
13115 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI			0x4
13116 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE			0x8
13134 #define NVM_CFG1_PORT_DCBX_MODE_MASK				0x000f0000
13136 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED			0x0
13137 #define NVM_CFG1_PORT_DCBX_MODE_IEEE				0x1
13138 #define NVM_CFG1_PORT_DCBX_MODE_CEE				0x2
13139 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC				0x3
13140 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK		0x00f00000
13142 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET	0x1
13143 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE		0x2
13144 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI		0x4
13150 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK		0x0000ffff
13151 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET		0
13152 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G		0x1
13153 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G		0x2
13154 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G		0x4
13155 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G		0x8
13156 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G		0x10
13157 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G		0x20
13158 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G		0x40
13161 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK			0x0000000f
13162 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET			0
13163 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG			0x0
13164 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G				0x1
13165 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G			0x2
13166 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G			0x3
13167 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G			0x4
13168 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G			0x5
13169 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G			0x6
13170 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G			0x7
13171 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ			0x8
13172 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK			0x00000070
13174 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG			0x1
13175 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX			0x2
13176 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX			0x4
13177 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK			0x000e0000
13179 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE			0x0
13180 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE			0x1
13181 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS				0x2
13182 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO			0x7
13189 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK		0x00ff0000
13191 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED		0x0
13192 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED		0x1
13193 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE		0x2
13194 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY		0x3
13205 #define NVM_CFG1_PORT_PORT_TYPE_MASK				0x000000ff
13206 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET				0
13207 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED			0x0
13208 #define NVM_CFG1_PORT_PORT_TYPE_MODULE				0x1
13209 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE			0x2
13210 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY				0x3
13211 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE			0x4
13233 #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK			0x0000ffff
13234 #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET			0
13235 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN		0x1
13236 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G		0x2
13237 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G		0x4
13238 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G		0x8
13239 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G		0x10
13240 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G		0x20
13241 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R		0x40
13242 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2		0x80
13243 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2		0x100
13244 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4		0x200
13245 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4		0x400
13246 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK			0xffff0000
13248 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED	0x1
13249 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G		0x2
13250 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G		0x4
13251 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G		0x8
13252 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G		0x10
13253 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G		0x20
13254 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R	0x40
13255 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2	0x80
13256 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2	0x100
13257 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4	0x200
13258 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4	0x400
13330 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)
13331 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)
13332 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)
13334 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)
13336 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)
13343 #define NVM_MAGIC_VALUE		0x669955aa
13346 	NVM_TYPE_TIM1 = 0x01,
13347 	NVM_TYPE_TIM2 = 0x02,
13348 	NVM_TYPE_MIM1 = 0x03,
13349 	NVM_TYPE_MIM2 = 0x04,
13350 	NVM_TYPE_MBA = 0x05,
13351 	NVM_TYPE_MODULES_PN = 0x06,
13352 	NVM_TYPE_VPD = 0x07,
13353 	NVM_TYPE_MFW_TRACE1 = 0x08,
13354 	NVM_TYPE_MFW_TRACE2 = 0x09,
13355 	NVM_TYPE_NVM_CFG1 = 0x0a,
13356 	NVM_TYPE_L2B = 0x0b,
13357 	NVM_TYPE_DIR1 = 0x0c,
13358 	NVM_TYPE_EAGLE_FW1 = 0x0d,
13359 	NVM_TYPE_FALCON_FW1 = 0x0e,
13360 	NVM_TYPE_PCIE_FW1 = 0x0f,
13361 	NVM_TYPE_HW_SET = 0x10,
13362 	NVM_TYPE_LIM = 0x11,
13363 	NVM_TYPE_AVS_FW1 = 0x12,
13364 	NVM_TYPE_DIR2 = 0x13,
13365 	NVM_TYPE_CCM = 0x14,
13366 	NVM_TYPE_EAGLE_FW2 = 0x15,
13367 	NVM_TYPE_FALCON_FW2 = 0x16,
13368 	NVM_TYPE_PCIE_FW2 = 0x17,
13369 	NVM_TYPE_AVS_FW2 = 0x18,
13370 	NVM_TYPE_INIT_HW = 0x19,
13371 	NVM_TYPE_DEFAULT_CFG = 0x1a,
13372 	NVM_TYPE_MDUMP = 0x1b,
13373 	NVM_TYPE_META = 0x1c,
13374 	NVM_TYPE_ISCSI_CFG = 0x1d,
13375 	NVM_TYPE_FCOE_CFG = 0x1f,
13376 	NVM_TYPE_ETH_PHY_FW1 = 0x20,
13377 	NVM_TYPE_ETH_PHY_FW2 = 0x21,
13378 	NVM_TYPE_BDN = 0x22,
13379 	NVM_TYPE_8485X_PHY_FW = 0x23,
13380 	NVM_TYPE_PUB_KEY = 0x24,
13381 	NVM_TYPE_RECOVERY = 0x25,
13382 	NVM_TYPE_PLDM = 0x26,
13383 	NVM_TYPE_UPK1 = 0x27,
13384 	NVM_TYPE_UPK2 = 0x28,
13385 	NVM_TYPE_MASTER_KC = 0x29,
13386 	NVM_TYPE_BACKUP_KC = 0x2a,
13387 	NVM_TYPE_HW_DUMP = 0x2b,
13388 	NVM_TYPE_HW_DUMP_OUT = 0x2c,
13389 	NVM_TYPE_BIN_NVM_META = 0x30,
13390 	NVM_TYPE_ROM_TEST = 0xf0,
13391 	NVM_TYPE_88X33X0_PHY_FW = 0x31,
13392 	NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
13396 #define DIR_ID_1    (0)