Searched +full:0 +full:x20030000 (Results 1 – 11 of 11) sorted by relevance
16 reg = <0x20030000 0x4000>;
11 #define MSM_DSI_VER_MAJOR_V2 0x0212 #define MSM_DSI_VER_MAJOR_6G 0x0313 #define MSM_DSI_6G_VER_MINOR_V1_0 0x1000000014 #define MSM_DSI_6G_VER_MINOR_V1_1 0x1001000015 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x1001000116 #define MSM_DSI_6G_VER_MINOR_V1_2 0x1002000017 #define MSM_DSI_6G_VER_MINOR_V1_3 0x1003000018 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x1003000119 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x1004000120 #define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002[all …]
98 reg = <0x20030000 0x10>;
159 reg = <0 0x20010000 0 0x1000>;165 etb_in_port: endpoint@0 {174 reg = <0 0x20030000 0 0x1000>;180 tpiu_in_port: endpoint@0 {189 reg = <0 0x20070000 0 0x1000>;219 #size-cells = <0>;222 port@0 {223 reg = <0>;265 #size-cells = <0>;267 port@0 {[all …]
35 #clock-cells = <0>;41 reg = <0x10090000 0x10000>;52 reg = <0x10104000 0x800>;64 reg = <0x10138000 0x1000>;71 reg = <0x1013c000 0x100>;76 reg = <0x1013c200 0x20>;83 reg = <0x1013c600 0x20>;92 reg = <0x1013d000 0x1000>,93 <0x1013c100 0x0100>;98 reg = <0x10124000 0x400>;[all …]
16 arm,hbi = <0x249>;17 arm,vexpress,site = <0xf>;36 #size-cells = <0>;38 cpu0: cpu@0 {41 reg = <0>;61 reg = <0x100>;71 reg = <0x101>;81 reg = <0x102>;109 reg = <0 0x80000000 0 0x40000000>;117 /* Chipselect 2 is physically at 0x18000000 */[all …]
34 #size-cells = <0>;40 reg = <0xf00>;53 reg = <0xf01>;84 #clock-cells = <0>;89 reg = <0x10080000 0x2000>;92 ranges = <0 0x10080000 0x2000>;94 smp-sram@0 {96 reg = <0x00 0x10>;102 reg = <0x10090000 0x10000>;122 reg = <0x10108000 0x800>;[all …]
29 #size-cells = <0>;34 reg = <0xf00>;85 #clock-cells = <0>;96 reg = <0x102a0000 0x4000>;97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;108 reg = <0x10080000 0x2000>;111 ranges = <0 0x10080000 0x2000>;116 reg = <0x10210000 0x100>;125 pinctrl-0 = <&uart2m0_xfer>;131 reg = <0x10220000 0x100>;[all …]
26 #size-cells = <0>;31 reg = <0xf00>;43 reg = <0xf01>;53 reg = <0xf02>;63 reg = <0xf03>;127 #clock-cells = <0>;137 reg = <0x100b0000 0x4000>;144 pinctrl-0 = <&i2s1_bus>;150 reg = <0x100c0000 0x4000>;161 reg = <0x100d0000 0x1000>;[all …]
12 reg = <0x0 0x2a810000 0x0 0x10000>;16 ranges = <0 0x0 0x2a820000 0x20000>;21 reg = <0x10000 0x10000>;27 reg = <0x0 0x2b1f0000 0x0 0x1000>;37 reg = <0x0 0x2b400000 0x0 0x10000>;49 reg = <0x0 0x2b500000 0x0 0x10000>;60 reg = <0x0 0x2b600000 0x0 0x10000>;66 power-domains = <&scpi_devpd 0>;71 reg = <0x0 0x2c010000 0 0x1000>,72 <0x0 0x2c02f000 0 0x2000>,[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x00 0x70000000 0x00 0x200000>;25 ranges = <0x0 0x00 0x70000000 0x200000>;28 reg = <0x1c0000 0x20000>;32 reg = <0x1e0000 0x1c000>;36 reg = <0x1fc000 0x4000>;42 reg = <0x0 0x43000000 0x0 0x20000>;45 ranges = <0x0 0x0 0x43000000 0x20000>;50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */[all …]
