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/Linux-v6.1/arch/sh/boards/mach-sh03/
Dsetup.c26 [0] = {
27 .start = 0x1f0,
28 .end = 0x1f0 + 8,
32 .start = 0x1f0 + 0x206,
33 .end = 0x1f0 +8 + 0x206 + 8,
50 [0] = {
51 .start = 0xa0800000,
52 .end = 0xa0800000,
84 /* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */ in sh03_devices_setup()
85 cf_ide_resources[0].start += (unsigned long)cf_ide_base; in sh03_devices_setup()
[all …]
/Linux-v6.1/arch/sh/boards/mach-lboxre2/
Dsetup.c19 [0] = {
20 .start = 0x1f0,
21 .end = 0x1f0 + 8 ,
25 .start = 0x1f0 + 0x206,
26 .end = 0x1f0 +8 + 0x206 + 8,
62 cf_ide_resources[0].start += cf0_io_base ; in lboxre2_devices_setup()
63 cf_ide_resources[0].end += cf0_io_base ; in lboxre2_devices_setup()
/Linux-v6.1/arch/sh/boards/mach-se/7721/
Dsetup.c41 [0] = {
42 .start = PA_MRSHPC_IO + 0x1f0,
43 .end = PA_MRSHPC_IO + 0x1f0 + 8 ,
47 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
48 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
79 __raw_writew(0x0000, 0xA405010C); /* PGCR */ in se7721_setup()
80 __raw_writew(0x0000, 0xA405010E); /* PHCR */ in se7721_setup()
81 __raw_writew(0x00AA, 0xA4050118); /* PPCR */ in se7721_setup()
82 __raw_writew(0x0000, 0xA4050124); /* PSELA */ in se7721_setup()
/Linux-v6.1/arch/sh/boards/mach-se/7722/
Dsetup.c46 [0] = {
48 .start = PA_LAN + 0x300,
49 .end = PA_LAN + 0x300 + 0x10 ,
60 .id = 0,
63 .coherent_dma_mask = 0xffffffff,
71 [0] = {
72 .start = PA_MRSHPC_IO + 0x1f0,
73 .end = PA_MRSHPC_IO + 0x1f0 + 8 ,
77 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
78 .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
[all …]
/Linux-v6.1/arch/sh/boards/mach-se/770x/
Dsetup.c37 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
42 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ in smsc_setup()
43 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ in smsc_setup()
47 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
48 smsc_config(IO_BASE_HI_INDEX, 0x03); in smsc_setup()
49 smsc_config(IO_BASE_LO_INDEX, 0xf8); in smsc_setup()
54 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
55 smsc_config(IO_BASE_HI_INDEX, 0x02); in smsc_setup()
56 smsc_config(IO_BASE_LO_INDEX, 0xf8); in smsc_setup()
61 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
[all …]
/Linux-v6.1/drivers/misc/habanalabs/include/gaudi/asic_reg/
Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/Linux-v6.1/arch/sh/boards/mach-hp6xx/
Dsetup.c21 #define SCPCR 0xa4000116
22 #define SCPDR 0xa4000136
26 [0] = {
27 .start = 0x15000000 + 0x1f0,
28 .end = 0x15000000 + 0x1f0 + 0x08 - 0x01,
32 .start = 0x15000000 + 0x1fe,
33 .end = 0x15000000 + 0x1fe + 0x01,
37 .start = evt2irq(0xba0),
87 sh_dac_output(0, pdata->channel); in dac_audio_stop()
149 sh_dac_output(0, DAC_SPEAKER_VOLUME); in hp6xx_setup()
/Linux-v6.1/drivers/ata/
Dpata_legacy.c70 module_param(probe_all, int, 0);
74 static int probe_mask = ~0;
75 module_param(probe_mask, int, 0);
79 module_param(autospeed, int, 0);
83 module_param(pio_mask, int, 0);
86 static int iordy_mask = 0xFFFFFFFF;
87 module_param(iordy_mask, int, 0);
91 module_param(ht6560a, int, 0);
95 module_param(ht6560b, int, 0);
99 module_param(opti82c611a, int, 0);
[all …]
/Linux-v6.1/drivers/misc/habanalabs/include/gaudi2/asic_reg/
Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx53-tx53.dtsi55 reg = <0x70000000 0>;
69 clock-frequency = <0>;
75 #clock-cells = <0>;
82 pinctrl-0 = <&pinctrl_gpio_key>;
95 pinctrl-0 = <&pinctrl_stk5led>;
124 pinctrl-0 = <&pinctrl_can_xcvr>;
134 pinctrl-0 = <&pinctrl_usbh1_vbus>;
145 pinctrl-0 = <&pinctrl_usbotg_vbus>;
167 pinctrl-0 = <&pinctrl_ssi1>;
173 pinctrl-0 = <&pinctrl_can1>;
[all …]
Dimx53-tx53-x13x.dts64 pwms = <&pwm2 0 500000 0>;
67 0 1 2 3 4 5 6 7 8 9
84 pwms = <&pwm1 0 500000 0>;
87 0 1 2 3 4 5 6 7 8 9
125 pinctrl-0 = <&pinctrl_i2c3>;
133 reg = <0x0a>;
134 #sound-dai-cells = <0>;
145 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
146 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
147 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
[all …]
Dimx53-tx53-x03x.dts60 pinctrl-0 = <&pinctrl_rgb24_vga1>;
80 hsync-active = <0>;
81 vsync-active = <0>;
83 pixelclk-active = <0>;
96 hsync-active = <0>;
97 vsync-active = <0>;
99 pixelclk-active = <0>;
112 hsync-active = <0>;
113 vsync-active = <0>;
115 pixelclk-active = <0>;
[all …]
/Linux-v6.1/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/Linux-v6.1/arch/arm64/boot/dts/marvell/
Dac5-98dx25xx.dtsi21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
84 /* 16M internal register @ 0x7f00_0000 */
85 ranges = <0x0 0x0 0x7f000000 0x1000000>;
90 reg = <0x12000 0x100>;
100 reg = <0x11000 0x100>;
110 reg = <0x12200 0x100>;
120 reg = <0x12300 0x100>;
[all …]
/Linux-v6.1/arch/sh/include/mach-common/mach/
Dr2d.h15 #define PA_BCR 0xa4000000 /* FPGA */
16 #define PA_IRLMON 0xa4000002 /* Interrupt Status control */
17 #define PA_CFCTL 0xa4000004 /* CF Timing control */
18 #define PA_CFPOW 0xa4000006 /* CF Power control */
19 #define PA_DISPCTL 0xa4000008 /* Display Timing control */
20 #define PA_SDMPOW 0xa400000a /* SD Power control */
21 #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
22 #define PA_PCICD 0xa400000e /* PCI Extension detect control */
23 #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
25 #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
[all …]
/Linux-v6.1/arch/sh/boards/mach-landisk/
Dsetup.c23 __raw_writeb(0x01, PA_SHUTDOWN); in landisk_power_off()
67 /* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */ in landisk_devices_setup()
68 cf_ide_resources[0].start = (unsigned long)cf_ide_base + 0x40; in landisk_devices_setup()
69 cf_ide_resources[0].end = (unsigned long)cf_ide_base + 0x40 + 0x0f; in landisk_devices_setup()
70 cf_ide_resources[0].flags = IORESOURCE_IO; in landisk_devices_setup()
71 cf_ide_resources[1].start = (unsigned long)cf_ide_base + 0x2c; in landisk_devices_setup()
72 cf_ide_resources[1].end = (unsigned long)cf_ide_base + 0x2c + 0x03; in landisk_devices_setup()
86 __set_io_port_base(0); in landisk_setup()
89 __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED); in landisk_setup()
/Linux-v6.1/drivers/pinctrl/
Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]

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