Lines Matching +full:0 +full:x1f0
21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
84 /* 16M internal register @ 0x7f00_0000 */
85 ranges = <0x0 0x0 0x7f000000 0x1000000>;
90 reg = <0x12000 0x100>;
100 reg = <0x11000 0x100>;
110 reg = <0x12200 0x100>;
120 reg = <0x12300 0x100>;
130 #size-cells = <0>;
132 reg = <0x22004 0x4>;
138 reg = <0x11000 0x20>;
140 #size-cells = <0>;
148 pinctrl-0 = <&i2c0_pins>;
157 reg = <0x11100 0x20>;
159 #size-cells = <0>;
167 pinctrl-0 = <&i2c1_pins>;
176 reg = <0x18100 0x40>;
180 gpio-ranges = <&pinctrl0 0 0 32>;
181 marvell,pwm-offset = <0x1f0>;
191 reg = <0x18140 0x40>;
196 gpio-ranges = <&pinctrl0 0 32 14>;
197 marvell,pwm-offset = <0x1f0>;
211 #address-cells = <0x2>;
212 #size-cells = <0x2>;
213 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
214 /* Host phy ram starts at 0x200M */
215 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
220 reg = <0x0 0x20000 0x0 0x4000>;
229 reg = <0x0 0x24000 0x0 0x4000>;
238 reg = <0x0 0x80000 0x0 0x500>;
245 reg = <0x0 0xa0000 0x0 0x500>;
253 reg = <0 0x80020100 0 0x20>;
278 reg = <0x0 0x805a0000 0x0 0x50>;
279 #address-cells = <0x1>;
280 #size-cells = <0x0>;
289 reg = <0x0 0x805a8000 0x0 0x50>;
290 #address-cells = <0x1>;
291 #size-cells = <0x0>;
302 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
303 <0x0 0x80660000 0x0 0x40000>; /* GICR */
311 #clock-cells = <0>;
317 #clock-cells = <0>;