Home
last modified time | relevance | path

Searched +full:0 +full:x1300000 (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/arm/msm/
Dqcom,llcc.yaml57 reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
/Linux-v5.15/arch/arm/boot/dts/
Dnuvoton-npcm750-evb.dts50 reg = <0x0 0x20000000>;
70 spi-nor@0 {
75 reg = <0>;
81 bbuboot1@0 {
83 reg = <0x0000000 0x80000>;
88 reg = <0x0080000 0x80000>;
93 reg = <0x0100000 0x40000>;
98 reg = <0x0140000 0xC0000>;
102 reg = <0x0200000 0x400000>;
106 reg = <0x0600000 0x700000>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
61 interrupts = <1 9 0x4>;
66 reg = <0x0 0x6020000 0 0x20000>;
[all …]
Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39 reg = <0x1>;
41 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 arm,psci-suspend-param = <0x0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
85 reg = <0x0 0xf1f0000 0x0 0xffff>;
[all …]
Dfsl-lx2160a.dtsi12 /memreserve/ 0x80000000 0x00010000;
26 #size-cells = <0>;
29 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
38 i-cache-size = <0xC000>;
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
[all …]
/Linux-v5.15/drivers/crypto/cavium/nitrox/
Dnitrox_csr.h21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000))
22 #define UCD_BIST_STATUS 0x12C0070
23 #define NPS_CORE_BIST_REG 0x10000E8
24 #define NPS_CORE_NPC_BIST_REG 0x1000128
25 #define NPS_PKT_SLC_BIST_REG 0x1040088
26 #define NPS_PKT_IN_BIST_REG 0x1040100
27 #define POM_BIST_REG 0x11C0100
28 #define BMI_BIST_REG 0x1140080
29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400))
30 #define EFL_TOP_BIST_STAT 0x1241090
[all …]
/Linux-v5.15/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.c15 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
19 #define CRB_BLK(off) ((off >> 20) & 0x3f)
20 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21 #define CRB_WINDOW_2M (0x130060)
22 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23 #define CRB_INDIRECT_2M (0x1e0000UL)
52 {{{0, 0, 0, 0} } }, /* 0: PCI */
53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
54 {1, 0x0110000, 0x0120000, 0x130000},
55 {1, 0x0120000, 0x0122000, 0x124000},
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]
Ddcn_3_1_2_offset.h27 // base address: 0x1300000
28 …CONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000
30 …CONTROLLER0_MINOR_VERSION 0x4b7000
32 …CONTROLLER0_MAJOR_VERSION 0x4b7000
34 …CONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001
36 …CONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001
38 …CONTROLLER0_GLOBAL_CONTROL 0x4b7002
40 …CONTROLLER0_WAKE_ENABLE 0x4b7003
42 …CONTROLLER0_STATE_CHANGE_STATUS 0x4b7003
44 …CONTROLLER0_GLOBAL_STATUS 0x4b7004
[all …]
/Linux-v5.15/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic_hw.c16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
22 #define CRB_BLK(off) ((off >> 20) & 0x3f)
23 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
24 #define CRB_WINDOW_2M (0x130060)
25 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
26 #define CRB_INDIRECT_2M (0x1e0000UL)
57 {{{0, 0, 0, 0} } }, /* 0: PCI */
58 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
[all …]
/Linux-v5.15/drivers/scsi/qla2xxx/
Dqla_nx.c15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
[all …]
/Linux-v5.15/drivers/scsi/qla4xxx/
Dql4_nx.c18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
[all …]