Lines Matching +full:0 +full:x1300000
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33 ((off) & 0xf0000))
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
46 0x410000A8, 0x410000AC,
47 0x410000B8, 0x410000BC
111 {{{0, 0, 0, 0} } },
112 {{{1, 0x0100000, 0x0102000, 0x120000},
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } } ,
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },
129 {{{0, 0, 0, 0} } },
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
134 {{{1, 0x0800000, 0x0802000, 0x170000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },
209 {{{0, 0, 0, 0} } },
210 {{{0, 0, 0, 0} } },
211 {{{0, 0, 0, 0} } },
212 {{{0, 0, 0, 0} } },
213 {{{0, 0, 0, 0} } },
214 {{{0, 0, 0, 0} } },
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
218 {{{0} } },
219 {{{1, 0x2100000, 0x2102000, 0x120000},
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{0} } },
237 {{{0} } },
238 {{{0} } },
239 {{{0} } },
240 {{{0} } },
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
253 {{{0} } },
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
260 {{{0} } },
261 {{{0} } },
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
271 0,
275 0,
298 0,
301 0,
303 0,
306 0,
307 0,
308 0,
309 0,
310 0,
312 0,
323 0,
328 0,
332 0,
334 0,
374 ql_dbg(ql_dbg_p3p, vha, 0xb000, in qla82xx_pci_set_crbwindow_2M()
375 "%s: Written crbwin (0x%x) " in qla82xx_pci_set_crbwindow_2M()
376 "!= Read crbwin (0x%x), off=0x%lx.\n", in qla82xx_pci_set_crbwindow_2M()
394 return 0; in qla82xx_pci_get_crb_addr_2M()
407 return 0; in qla82xx_pci_get_crb_addr_2M()
417 int done = 0, timeout = 0; in qla82xx_crb_win_lock()
429 return 0; in qla82xx_crb_win_lock()
436 unsigned long flags = 0; in qla82xx_wr_32()
459 return 0; in qla82xx_wr_32()
466 unsigned long flags = 0; in qla82xx_rd_32()
498 int done, total = 0; in qla82xx_idc_lock()
514 return 0; in qla82xx_idc_lock()
535 return 0; in qla82xx_pci_mem_bound_check()
559 ql_dbg(ql_dbg_p3p, vha, 0xb003, in qla82xx_pci_set_window()
560 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", in qla82xx_pci_set_window()
568 if ((addr & 0x00ff800) == 0xff800) { in qla82xx_pci_set_window()
569 ql_log(ql_log_warn, vha, 0xb004, in qla82xx_pci_set_window()
579 temp1 = ((window & 0x1FF) << 7) | in qla82xx_pci_set_window()
580 ((window & 0x0FFFE0000) >> 17); in qla82xx_pci_set_window()
582 ql_log(ql_log_warn, vha, 0xb005, in qla82xx_pci_set_window()
583 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", in qla82xx_pci_set_window()
598 ql_log(ql_log_warn, vha, 0xb006, in qla82xx_pci_set_window()
599 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", in qla82xx_pci_set_window()
609 (qla82xx_pci_set_window_warning_count%64 == 0)) { in qla82xx_pci_set_window()
610 ql_log(ql_log_warn, vha, 0xb007, in qla82xx_pci_set_window()
640 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; in qla82xx_pci_is_same_window()
644 return 0; in qla82xx_pci_is_same_window()
652 int ret = 0; in qla82xx_pci_mem_read_direct()
667 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_read_direct()
669 ql_log(ql_log_fatal, vha, 0xb008, in qla82xx_pci_mem_read_direct()
671 "access, offset is 0x%llx.\n", in qla82xx_pci_mem_read_direct()
677 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_read_direct()
687 *(u8 *)data = 0; in qla82xx_pci_mem_read_direct()
724 int ret = 0; in qla82xx_pci_mem_write_direct()
739 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_write_direct()
741 ql_log(ql_log_fatal, vha, 0xb009, in qla82xx_pci_mem_write_direct()
743 "access, offset is 0x%llx.\n", in qla82xx_pci_mem_write_direct()
749 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_write_direct()
799 base_addr = addr & 0xfff00000; in qla82xx_decode_crb_addr()
800 offset = addr & 0x000fffff; in qla82xx_decode_crb_addr()
802 for (i = 0; i < MAX_CRB_XFORM; i++) { in qla82xx_decode_crb_addr()
819 int done = 0, timeout = 0; in qla82xx_rom_lock()
820 uint32_t lock_owner = 0; in qla82xx_rom_lock()
830 ql_dbg(ql_dbg_p3p, vha, 0xb157, in qla82xx_rom_lock()
838 return 0; in qla82xx_rom_lock()
844 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); in qla82xx_rom_unlock()
851 long timeout = 0; in qla82xx_wait_rom_busy()
852 long done = 0 ; in qla82xx_wait_rom_busy()
855 while (done == 0) { in qla82xx_wait_rom_busy()
860 ql_dbg(ql_dbg_p3p, vha, 0xb00a, in qla82xx_wait_rom_busy()
866 return 0; in qla82xx_wait_rom_busy()
872 long timeout = 0; in qla82xx_wait_rom_done()
873 long done = 0 ; in qla82xx_wait_rom_done()
876 while (done == 0) { in qla82xx_wait_rom_done()
881 ql_dbg(ql_dbg_p3p, vha, 0xb00b, in qla82xx_wait_rom_done()
887 return 0; in qla82xx_wait_rom_done()
893 uint32_t off_value, rval = 0; in qla82xx_md_rw_32()
895 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); in qla82xx_md_rw_32()
899 off_value = (off & 0x0000FFFF); in qla82xx_md_rw_32()
915 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); in qla82xx_do_rom_fast_read()
917 (addr & 0x0000FFFF), 0, 0); in qla82xx_do_rom_fast_read()
919 return 0; in qla82xx_do_rom_fast_read()
925 int ret, loops = 0; in qla82xx_rom_fast_read()
926 uint32_t lock_owner = 0; in qla82xx_rom_fast_read()
929 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in qla82xx_rom_fast_read()
936 ql_log(ql_log_fatal, vha, 0x00b9, in qla82xx_rom_fast_read()
954 ql_log(ql_log_warn, vha, 0xb00c, in qla82xx_read_status_reg()
959 return 0; in qla82xx_read_status_reg()
965 uint32_t val = 0; in qla82xx_flash_wait_write_finish()
969 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_wait_write_finish()
970 for (i = 0; i < 50000; i++) { in qla82xx_flash_wait_write_finish()
972 if (ret < 0 || (val & 1) == 0) in qla82xx_flash_wait_write_finish()
977 ql_log(ql_log_warn, vha, 0xb00d, in qla82xx_flash_wait_write_finish()
988 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_set_write_enable()
993 if (qla82xx_read_status_reg(ha, &val) != 0) in qla82xx_flash_set_write_enable()
997 return 0; in qla82xx_flash_set_write_enable()
1008 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); in qla82xx_write_status_reg()
1010 ql_log(ql_log_warn, vha, 0xb00e, in qla82xx_write_status_reg()
1024 ql_log(ql_log_warn, vha, 0xb00f, in qla82xx_write_disable_flash()
1028 return 0; in qla82xx_write_disable_flash()
1034 int loops = 0; in ql82xx_rom_lock_d()
1035 uint32_t lock_owner = 0; in ql82xx_rom_lock_d()
1038 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in ql82xx_rom_lock_d()
1045 ql_log(ql_log_warn, vha, 0xb010, in ql82xx_rom_lock_d()
1049 return 0; in ql82xx_rom_lock_d()
1056 int ret = 0; in qla82xx_write_flash_dword()
1060 if (ret < 0) { in qla82xx_write_flash_dword()
1061 ql_log(ql_log_warn, vha, 0xb011, in qla82xx_write_flash_dword()
1067 if (ret < 0) in qla82xx_write_flash_dword()
1076 ql_log(ql_log_warn, vha, 0xb012, in qla82xx_write_flash_dword()
1111 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); in qla82xx_pinit_from_rom()
1112 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); in qla82xx_pinit_from_rom()
1113 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); in qla82xx_pinit_from_rom()
1114 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); in qla82xx_pinit_from_rom()
1115 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); in qla82xx_pinit_from_rom()
1116 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); in qla82xx_pinit_from_rom()
1119 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); in qla82xx_pinit_from_rom()
1121 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); in qla82xx_pinit_from_rom()
1123 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); in qla82xx_pinit_from_rom()
1125 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); in qla82xx_pinit_from_rom()
1127 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); in qla82xx_pinit_from_rom()
1129 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); in qla82xx_pinit_from_rom()
1132 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); in qla82xx_pinit_from_rom()
1133 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); in qla82xx_pinit_from_rom()
1136 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); in qla82xx_pinit_from_rom()
1139 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); in qla82xx_pinit_from_rom()
1140 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); in qla82xx_pinit_from_rom()
1141 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); in qla82xx_pinit_from_rom()
1142 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); in qla82xx_pinit_from_rom()
1143 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); in qla82xx_pinit_from_rom()
1144 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); in qla82xx_pinit_from_rom()
1147 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); in qla82xx_pinit_from_rom()
1148 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); in qla82xx_pinit_from_rom()
1149 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); in qla82xx_pinit_from_rom()
1150 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); in qla82xx_pinit_from_rom()
1151 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); in qla82xx_pinit_from_rom()
1157 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); in qla82xx_pinit_from_rom()
1159 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); in qla82xx_pinit_from_rom()
1163 * Offset 0: Contain signature (0xcafecafe) in qla82xx_pinit_from_rom()
1167 n = 0; in qla82xx_pinit_from_rom()
1168 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || in qla82xx_pinit_from_rom()
1169 qla82xx_rom_fast_read(ha, 4, &n) != 0) { in qla82xx_pinit_from_rom()
1170 ql_log(ql_log_fatal, vha, 0x006e, in qla82xx_pinit_from_rom()
1178 offset = n & 0xffffU; in qla82xx_pinit_from_rom()
1179 n = (n >> 16) & 0xffffU; in qla82xx_pinit_from_rom()
1183 ql_log(ql_log_fatal, vha, 0x0071, in qla82xx_pinit_from_rom()
1184 "Card flash not initialized:n=0x%x.\n", n); in qla82xx_pinit_from_rom()
1188 ql_log(ql_log_info, vha, 0x0072, in qla82xx_pinit_from_rom()
1193 ql_log(ql_log_fatal, vha, 0x010c, in qla82xx_pinit_from_rom()
1198 for (i = 0; i < n; i++) { in qla82xx_pinit_from_rom()
1199 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || in qla82xx_pinit_from_rom()
1200 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { in qla82xx_pinit_from_rom()
1209 for (i = 0; i < n; i++) { in qla82xx_pinit_from_rom()
1220 if (off == QLA82XX_CAM_RAM(0x1fc)) in qla82xx_pinit_from_rom()
1224 if (off == (ROMUSB_GLB + 0xbc)) in qla82xx_pinit_from_rom()
1228 if (off == (ROMUSB_GLB + 0xc8)) in qla82xx_pinit_from_rom()
1238 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) in qla82xx_pinit_from_rom()
1241 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) in qla82xx_pinit_from_rom()
1245 ql_log(ql_log_fatal, vha, 0x0116, in qla82xx_pinit_from_rom()
1246 "Unknown addr: 0x%08lx.\n", buf[i].addr); in qla82xx_pinit_from_rom()
1253 * else crb_window returns 0xffffffff in qla82xx_pinit_from_rom()
1267 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); in qla82xx_pinit_from_rom()
1268 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); in qla82xx_pinit_from_rom()
1269 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); in qla82xx_pinit_from_rom()
1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); in qla82xx_pinit_from_rom()
1273 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); in qla82xx_pinit_from_rom()
1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); in qla82xx_pinit_from_rom()
1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); in qla82xx_pinit_from_rom()
1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); in qla82xx_pinit_from_rom()
1277 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); in qla82xx_pinit_from_rom()
1278 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); in qla82xx_pinit_from_rom()
1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); in qla82xx_pinit_from_rom()
1280 return 0; in qla82xx_pinit_from_rom()
1287 int i, j, ret = 0, loop, sz[2], off0; in qla82xx_pci_mem_write_2M()
1290 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; in qla82xx_pci_mem_write_2M()
1299 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_write_2M()
1304 off0 = off & 0x7; in qla82xx_pci_mem_write_2M()
1305 sz[0] = (size < (8 - off0)) ? size : (8 - off0); in qla82xx_pci_mem_write_2M()
1306 sz[1] = size - sz[0]; in qla82xx_pci_mem_write_2M()
1308 off8 = off & 0xfffffff0; in qla82xx_pci_mem_write_2M()
1309 loop = (((off & 0xf) + size - 1) >> 4) + 1; in qla82xx_pci_mem_write_2M()
1312 startword = (off & 0xf)/8; in qla82xx_pci_mem_write_2M()
1314 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_write_2M()
1336 if (sz[0] == 8) { in qla82xx_pci_mem_write_2M()
1340 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); in qla82xx_pci_mem_write_2M()
1343 if (sz[1] != 0) { in qla82xx_pci_mem_write_2M()
1344 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); in qla82xx_pci_mem_write_2M()
1345 word[startword+1] |= tmpw >> (sz[0] * 8); in qla82xx_pci_mem_write_2M()
1348 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_write_2M()
1351 temp = 0; in qla82xx_pci_mem_write_2M()
1353 temp = word[i * scale] & 0xffffffff; in qla82xx_pci_mem_write_2M()
1355 temp = (word[i * scale] >> 32) & 0xffffffff; in qla82xx_pci_mem_write_2M()
1357 temp = word[i*scale + 1] & 0xffffffff; in qla82xx_pci_mem_write_2M()
1360 temp = (word[i*scale + 1] >> 32) & 0xffffffff; in qla82xx_pci_mem_write_2M()
1369 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_pci_mem_write_2M()
1371 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla82xx_pci_mem_write_2M()
1391 long size = 0; in qla82xx_fw_load_from_flash()
1399 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_flash()
1409 if (i % 0x1000 == 0) in qla82xx_fw_load_from_flash()
1414 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_flash()
1415 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_flash()
1417 return 0; in qla82xx_fw_load_from_flash()
1424 int i, j = 0, k, start, end, loop, sz[2], off0[2]; in qla82xx_pci_mem_read_2M()
1427 uint64_t off8, val, mem_crb, word[2] = {0, 0}; in qla82xx_pci_mem_read_2M()
1437 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_read_2M()
1442 off8 = off & 0xfffffff0; in qla82xx_pci_mem_read_2M()
1443 off0[0] = off & 0xf; in qla82xx_pci_mem_read_2M()
1444 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); in qla82xx_pci_mem_read_2M()
1446 loop = ((off0[0] + size - 1) >> shift_amount) + 1; in qla82xx_pci_mem_read_2M()
1447 off0[1] = 0; in qla82xx_pci_mem_read_2M()
1448 sz[1] = size - sz[0]; in qla82xx_pci_mem_read_2M()
1450 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_read_2M()
1453 temp = 0; in qla82xx_pci_mem_read_2M()
1460 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_pci_mem_read_2M()
1462 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla82xx_pci_mem_read_2M()
1485 if ((off0[0] & 7) == 0) { in qla82xx_pci_mem_read_2M()
1486 val = word[0]; in qla82xx_pci_mem_read_2M()
1488 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | in qla82xx_pci_mem_read_2M()
1489 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); in qla82xx_pci_mem_read_2M()
1506 return 0; in qla82xx_pci_mem_read_2M()
1515 (struct qla82xx_uri_table_desc *)&unirom[0]; in qla82xx_get_table_desc()
1520 for (i = 0; i < entries; i++) { in qla82xx_get_table_desc()
1601 unsigned long val = 0; in qla82xx_pci_region_offset()
1605 case 0: in qla82xx_pci_region_offset()
1606 val = 0; in qla82xx_pci_region_offset()
1620 uint32_t len = 0; in qla82xx_iospace_config()
1623 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, in qla82xx_iospace_config()
1629 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { in qla82xx_iospace_config()
1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, in qla82xx_iospace_config()
1631 "Region #0 not an MMIO resource, aborting.\n"); in qla82xx_iospace_config()
1635 len = pci_resource_len(ha->pdev, 0); in qla82xx_iospace_config()
1636 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); in qla82xx_iospace_config()
1638 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, in qla82xx_iospace_config()
1647 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); in qla82xx_iospace_config()
1654 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, in qla82xx_iospace_config()
1672 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, in qla82xx_iospace_config()
1677 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, in qla82xx_iospace_config()
1682 return 0; in qla82xx_iospace_config()
1696 * Returns 0 on success.
1707 ql_dbg(ql_dbg_init, vha, 0x0043, in qla82xx_pci_config()
1710 return 0; in qla82xx_pci_config()
1717 * Returns 0 on success.
1734 struct req_que *req = ha->req_q_map[0]; in qla82xx_config_rings()
1735 struct rsp_que *rsp = ha->rsp_q_map[0]; in qla82xx_config_rings()
1739 icb->request_q_outpointer = cpu_to_le16(0); in qla82xx_config_rings()
1740 icb->response_q_inpointer = cpu_to_le16(0); in qla82xx_config_rings()
1746 wrt_reg_dword(®->req_q_out[0], 0); in qla82xx_config_rings()
1747 wrt_reg_dword(®->rsp_q_in[0], 0); in qla82xx_config_rings()
1748 wrt_reg_dword(®->rsp_q_out[0], 0); in qla82xx_config_rings()
1763 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_blob()
1774 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_blob()
1788 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); in qla82xx_fw_load_from_blob()
1791 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_blob()
1792 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_blob()
1794 return 0; in qla82xx_fw_load_from_blob()
1807 int mn_present = 0; in qla82xx_set_product_offset()
1817 for (i = 0; i < entries; i++) { in qla82xx_set_product_offset()
1829 return 0; in qla82xx_set_product_offset()
1860 return 0; in qla82xx_validate_firmware_blob()
1866 u32 val = 0; in qla82xx_check_cmdpeg_state()
1884 ql_log(ql_log_info, vha, 0x00a8, in qla82xx_check_cmdpeg_state()
1885 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", in qla82xx_check_cmdpeg_state()
1892 ql_log(ql_log_fatal, vha, 0x00a9, in qla82xx_check_cmdpeg_state()
1893 "Cmd Peg initialization failed: 0x%x.\n", val); in qla82xx_check_cmdpeg_state()
1905 u32 val = 0; in qla82xx_check_rcvpeg_state()
1923 ql_log(ql_log_info, vha, 0x00ab, in qla82xx_check_rcvpeg_state()
1924 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", in qla82xx_check_rcvpeg_state()
1931 ql_log(ql_log_fatal, vha, 0x00ac, in qla82xx_check_rcvpeg_state()
1932 "Rcv Peg initialization failed: 0x%x.\n", val); in qla82xx_check_rcvpeg_state()
1960 ha->mailbox_out[0] = mb0; in qla82xx_mbx_completion()
1968 ql_dbg(ql_dbg_async, vha, 0x5053, in qla82xx_mbx_completion()
1988 int status = 0, status1 = 0; in qla82xx_intr_handler()
1991 uint32_t stat = 0; in qla82xx_intr_handler()
1996 ql_log(ql_log_info, NULL, 0xb053, in qla82xx_intr_handler()
2013 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); in qla82xx_intr_handler()
2028 switch (stat & 0xff) { in qla82xx_intr_handler()
2029 case 0x1: in qla82xx_intr_handler()
2030 case 0x2: in qla82xx_intr_handler()
2031 case 0x10: in qla82xx_intr_handler()
2032 case 0x11: in qla82xx_intr_handler()
2036 case 0x12: in qla82xx_intr_handler()
2037 mb[0] = MSW(stat); in qla82xx_intr_handler()
2043 case 0x13: in qla82xx_intr_handler()
2047 ql_dbg(ql_dbg_async, vha, 0x5054, in qla82xx_intr_handler()
2049 stat & 0xff); in qla82xx_intr_handler()
2053 wrt_reg_dword(®->host_int, 0); in qla82xx_intr_handler()
2060 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_intr_handler()
2072 int status = 0; in qla82xx_msix_default()
2074 uint32_t stat = 0; in qla82xx_msix_default()
2075 uint32_t host_int = 0; in qla82xx_msix_default()
2097 switch (stat & 0xff) { in qla82xx_msix_default()
2098 case 0x1: in qla82xx_msix_default()
2099 case 0x2: in qla82xx_msix_default()
2100 case 0x10: in qla82xx_msix_default()
2101 case 0x11: in qla82xx_msix_default()
2105 case 0x12: in qla82xx_msix_default()
2106 mb[0] = MSW(stat); in qla82xx_msix_default()
2112 case 0x13: in qla82xx_msix_default()
2116 ql_dbg(ql_dbg_async, vha, 0x5041, in qla82xx_msix_default()
2118 stat & 0xff); in qla82xx_msix_default()
2122 wrt_reg_dword(®->host_int, 0); in qla82xx_msix_default()
2123 } while (0); in qla82xx_msix_default()
2139 uint32_t host_int = 0; in qla82xx_msix_rsp_q()
2156 wrt_reg_dword(®->host_int, 0); in qla82xx_msix_rsp_q()
2170 uint32_t host_int = 0; in qla82xx_poll()
2191 switch (stat & 0xff) { in qla82xx_poll()
2192 case 0x1: in qla82xx_poll()
2193 case 0x2: in qla82xx_poll()
2194 case 0x10: in qla82xx_poll()
2195 case 0x11: in qla82xx_poll()
2198 case 0x12: in qla82xx_poll()
2199 mb[0] = MSW(stat); in qla82xx_poll()
2205 case 0x13: in qla82xx_poll()
2209 ql_dbg(ql_dbg_p3p, vha, 0xb013, in qla82xx_poll()
2211 stat * 0xff); in qla82xx_poll()
2214 wrt_reg_dword(®->host_int, 0); in qla82xx_poll()
2228 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); in qla82xx_enable_intrs()
2230 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_enable_intrs()
2247 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); in qla82xx_disable_intrs()
2249 ha->interrupts_on = 0; in qla82xx_disable_intrs()
2280 ql_log(ql_log_info, vha, 0xb082, in qla82xx_set_idc_version()
2285 ql_log(ql_log_info, vha, 0xb083, in qla82xx_set_idc_version()
2301 if (drv_active == 0xffffffff) { in qla82xx_set_drv_active()
2344 if (drv_state == 0xffffffff) { in qla82xx_set_rst_ready()
2349 ql_dbg(ql_dbg_init, vha, 0x00bb, in qla82xx_set_rst_ready()
2350 "drv_state = 0x%08x.\n", drv_state); in qla82xx_set_rst_ready()
2393 ql_log(ql_log_fatal, vha, 0x009f, in qla82xx_load_fw()
2412 ql_log(ql_log_info, vha, 0x00a0, in qla82xx_load_fw()
2416 ql_log(ql_log_info, vha, 0x00a1, in qla82xx_load_fw()
2420 ql_log(ql_log_warn, vha, 0x0108, in qla82xx_load_fw()
2425 ql_log(ql_log_info, vha, 0x00a2, in qla82xx_load_fw()
2431 ql_log(ql_log_fatal, vha, 0x00a3, in qla82xx_load_fw()
2442 ql_log(ql_log_fatal, vha, 0x00a4, in qla82xx_load_fw()
2449 ql_log(ql_log_info, vha, 0x00a5, in qla82xx_load_fw()
2454 ql_log(ql_log_fatal, vha, 0x00a6, in qla82xx_load_fw()
2473 * of 0 before resetting the hardware in qla82xx_start_firmware()
2475 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); in qla82xx_start_firmware()
2476 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); in qla82xx_start_firmware()
2479 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); in qla82xx_start_firmware()
2480 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); in qla82xx_start_firmware()
2483 ql_log(ql_log_fatal, vha, 0x00a7, in qla82xx_start_firmware()
2490 ql_log(ql_log_fatal, vha, 0x00aa, in qla82xx_start_firmware()
2497 ha->link_width = (lnk >> 4) & 0x3f; in qla82xx_start_firmware()
2512 for (i = 0; i < length/4; i++, faddr += 4) { in qla82xx_read_flash_data()
2514 ql_log(ql_log_warn, vha, 0x0106, in qla82xx_read_flash_data()
2532 if (ret < 0) { in qla82xx_unprotect_flash()
2533 ql_log(ql_log_warn, vha, 0xb014, in qla82xx_unprotect_flash()
2539 if (ret < 0) in qla82xx_unprotect_flash()
2544 if (ret < 0) { in qla82xx_unprotect_flash()
2549 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_unprotect_flash()
2550 ql_log(ql_log_warn, vha, 0xb015, in qla82xx_unprotect_flash()
2566 if (ret < 0) { in qla82xx_protect_flash()
2567 ql_log(ql_log_warn, vha, 0xb016, in qla82xx_protect_flash()
2573 if (ret < 0) in qla82xx_protect_flash()
2579 if (ret < 0) in qla82xx_protect_flash()
2580 ql_log(ql_log_warn, vha, 0xb017, in qla82xx_protect_flash()
2583 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_protect_flash()
2584 ql_log(ql_log_warn, vha, 0xb018, in qla82xx_protect_flash()
2594 int ret = 0; in qla82xx_erase_sector()
2598 if (ret < 0) { in qla82xx_erase_sector()
2599 ql_log(ql_log_warn, vha, 0xb019, in qla82xx_erase_sector()
2610 ql_log(ql_log_warn, vha, 0xb01a, in qla82xx_erase_sector()
2643 int page_mode = 0; in qla82xx_write_flash_data()
2649 if (page_mode && !(faddr & 0xfff) && in qla82xx_write_flash_data()
2654 ql_log(ql_log_warn, vha, 0xb01b, in qla82xx_write_flash_data()
2665 ql_log(ql_log_warn, vha, 0xb01c, in qla82xx_write_flash_data()
2670 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { in qla82xx_write_flash_data()
2672 if ((faddr & rest_addr) == 0) { in qla82xx_write_flash_data()
2676 ql_log(ql_log_warn, vha, 0xb01d, in qla82xx_write_flash_data()
2692 ql_log(ql_log_warn, vha, 0xb01e, in qla82xx_write_flash_data()
2697 ql_log(ql_log_warn, vha, 0xb01f, in qla82xx_write_flash_data()
2714 ql_dbg(ql_dbg_p3p, vha, 0xb020, in qla82xx_write_flash_data()
2723 ql_log(ql_log_warn, vha, 0xb021, in qla82xx_write_flash_data()
2755 struct req_que *req = ha->req_q_map[0]; in qla82xx_start_iocbs()
2761 req->ring_index = 0; in qla82xx_start_iocbs()
2766 dbval = 0x04 | (ha->portnum << 5); in qla82xx_start_iocbs()
2785 uint32_t lock_owner = 0; in qla82xx_rom_lock_recovery()
2790 ql_log(ql_log_info, vha, 0xb022, in qla82xx_rom_lock_recovery()
2809 * Success : 0
2819 int need_reset = 0; in qla82xx_device_bootstrap()
2829 for (i = 0; i < 10; i++) { in qla82xx_device_bootstrap()
2841 ql_log(ql_log_info, vha, 0x009e, in qla82xx_device_bootstrap()
2850 ql_log(ql_log_fatal, vha, 0x00ad, in qla82xx_device_bootstrap()
2858 ql_log(ql_log_info, vha, 0x00ae, in qla82xx_device_bootstrap()
2896 drv_active = drv_active << 0x01; in qla82xx_need_qsnt_handler()
2904 ql_log(ql_log_info, vha, 0xb023, in qla82xx_need_qsnt_handler()
2910 ql_log(ql_log_info, vha, 0xb025, in qla82xx_need_qsnt_handler()
2926 drv_active = drv_active << 0x01; in qla82xx_need_qsnt_handler()
2931 ql_log(ql_log_info, vha, 0xb026, in qla82xx_need_qsnt_handler()
2969 ql_log(ql_log_fatal, vha, 0x00b8, in qla8xxx_dev_failed_handler()
2984 vha->flags.online = 0; in qla8xxx_dev_failed_handler()
2985 vha->flags.init_done = 0; in qla8xxx_dev_failed_handler()
2996 * Success : 0
3003 uint32_t active_mask = 0; in qla82xx_need_reset_handler()
3006 struct req_que *req = ha->req_q_map[0]; in qla82xx_need_reset_handler()
3018 ql_dbg(ql_dbg_p3p, vha, 0xb028, in qla82xx_need_reset_handler()
3019 "reset_acknowledged by 0x%x\n", ha->portnum); in qla82xx_need_reset_handler()
3024 ql_dbg(ql_dbg_p3p, vha, 0xb029, in qla82xx_need_reset_handler()
3025 "active_mask: 0x%08x\n", active_mask); in qla82xx_need_reset_handler()
3035 ql_dbg(ql_dbg_p3p, vha, 0xb02a, in qla82xx_need_reset_handler()
3036 "drv_state: 0x%08x, drv_active: 0x%08x, " in qla82xx_need_reset_handler()
3037 "dev_state: 0x%08x, active_mask: 0x%08x\n", in qla82xx_need_reset_handler()
3043 ql_log(ql_log_warn, vha, 0x00b5, in qla82xx_need_reset_handler()
3057 ql_dbg(ql_dbg_p3p, vha, 0xb02b, in qla82xx_need_reset_handler()
3058 "drv_state: 0x%08x, drv_active: 0x%08x, " in qla82xx_need_reset_handler()
3059 "dev_state: 0x%08x, active_mask: 0x%08x\n", in qla82xx_need_reset_handler()
3062 ql_log(ql_log_info, vha, 0x00b6, in qla82xx_need_reset_handler()
3063 "Device state is 0x%x = %s.\n", in qla82xx_need_reset_handler()
3070 ql_log(ql_log_info, vha, 0x00b7, in qla82xx_need_reset_handler()
3076 ql_log(ql_log_warn, vha, 0xb02c, in qla82xx_need_reset_handler()
3079 ql_log(ql_log_warn, vha, 0xb04f, in qla82xx_need_reset_handler()
3105 ql_dbg(ql_dbg_p3p, vha, 0xb02d, in qla82xx_check_md_needed()
3119 ql_log(ql_log_info, vha, 0xb02e, in qla82xx_check_md_needed()
3130 int status = 0; in qla82xx_check_fw_alive()
3134 /* all 0xff, assume AER/EEH in progress, ignore */ in qla82xx_check_fw_alive()
3135 if (fw_heartbeat_counter == 0xffffffff) { in qla82xx_check_fw_alive()
3136 ql_dbg(ql_dbg_timer, vha, 0x6003, in qla82xx_check_fw_alive()
3137 "FW heartbeat counter is 0xffffffff, " in qla82xx_check_fw_alive()
3145 vha->seconds_since_last_heartbeat = 0; in qla82xx_check_fw_alive()
3149 vha->seconds_since_last_heartbeat = 0; in qla82xx_check_fw_alive()
3152 ql_dbg(ql_dbg_timer, vha, 0x6004, in qla82xx_check_fw_alive()
3165 * Success : 0
3176 int loopcount = 0; in qla82xx_device_state_handler()
3186 ql_log(ql_log_info, vha, 0x009b, in qla82xx_device_state_handler()
3187 "Device state is 0x%x = %s.\n", in qla82xx_device_state_handler()
3197 ql_log(ql_log_fatal, vha, 0x009c, in qla82xx_device_state_handler()
3204 loopcount = 0; in qla82xx_device_state_handler()
3208 ql_log(ql_log_info, vha, 0x009d, in qla82xx_device_state_handler()
3209 "Device state is 0x%x = %s.\n", in qla82xx_device_state_handler()
3217 ha->flags.nic_core_reset_owner = 0; in qla82xx_device_state_handler()
3286 ql_log(ql_log_warn, vha, 0x600e, in qla82xx_check_temp()
3292 ql_log(ql_log_warn, vha, 0x600f, in qla82xx_check_temp()
3297 return 0; in qla82xx_check_temp()
3314 ha->flags.mbox_busy = 0; in qla82xx_clear_pending_mbx()
3315 ql_log(ql_log_warn, vha, 0x6010, in qla82xx_clear_pending_mbx()
3336 ql_log(ql_log_warn, vha, 0x6001, in qla82xx_watchdog()
3341 ql_log(ql_log_warn, vha, 0x6002, in qla82xx_watchdog()
3347 ql_log(ql_log_warn, vha, 0xb055, in qla82xx_watchdog()
3354 ql_dbg(ql_dbg_timer, vha, 0x6011, in qla82xx_watchdog()
3355 "disabling pause transmit on port 0 & 1.\n"); in qla82xx_watchdog()
3356 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, in qla82xx_watchdog()
3360 ql_log(ql_log_info, vha, 0x6005, in qla82xx_watchdog()
3362 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " in qla82xx_watchdog()
3363 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " in qla82xx_watchdog()
3364 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " in qla82xx_watchdog()
3365 " PEG_NET_4_PC: 0x%x.\n", halt_status, in qla82xx_watchdog()
3368 QLA82XX_CRB_PEG_NET_0 + 0x3c), in qla82xx_watchdog()
3370 QLA82XX_CRB_PEG_NET_1 + 0x3c), in qla82xx_watchdog()
3372 QLA82XX_CRB_PEG_NET_2 + 0x3c), in qla82xx_watchdog()
3374 QLA82XX_CRB_PEG_NET_3 + 0x3c), in qla82xx_watchdog()
3376 QLA82XX_CRB_PEG_NET_4 + 0x3c)); in qla82xx_watchdog()
3377 if (((halt_status & 0x1fffff00) >> 8) == 0x67) in qla82xx_watchdog()
3378 ql_log(ql_log_warn, vha, 0xb052, in qla82xx_watchdog()
3380 "error code 0x00006700. Device is " in qla82xx_watchdog()
3386 ql_log(ql_log_info, vha, 0x6006, in qla82xx_watchdog()
3392 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); in qla82xx_watchdog()
3420 uint32_t dev_state = 0; in qla82xx_set_reset_owner()
3428 ql_log(ql_log_info, vha, 0xb02f, in qla82xx_set_reset_owner()
3434 ql_dbg(ql_dbg_p3p, vha, 0xb030, in qla82xx_set_reset_owner()
3435 "reset_owner is 0x%x\n", ha->portnum); in qla82xx_set_reset_owner()
3440 ql_log(ql_log_info, vha, 0xb031, in qla82xx_set_reset_owner()
3441 "Device state is 0x%x = %s.\n", in qla82xx_set_reset_owner()
3454 * 0 = success
3463 ql_log(ql_log_warn, vha, 0x8024, in qla82xx_abort_isp()
3488 ha->flags.isp82xx_fw_hung = 0; in qla82xx_abort_isp()
3489 ha->flags.nic_core_reset_hdlr_active = 0; in qla82xx_abort_isp()
3496 if (ha->isp_abort_cnt == 0) { in qla82xx_abort_isp()
3497 ql_log(ql_log_warn, vha, 0x8027, in qla82xx_abort_isp()
3505 vha->flags.online = 0; in qla82xx_abort_isp()
3511 ql_log(ql_log_warn, vha, 0x8036, in qla82xx_abort_isp()
3518 ql_dbg(ql_dbg_taskm, vha, 0x8029, in qla82xx_abort_isp()
3539 * 0 = success
3570 * Success (fcoe_ctx reset is done) : 0
3592 ql_dbg(ql_dbg_p3p, vha, 0xb027, in qla2x00_wait_for_fcoe_ctx_reset()
3601 int i, fw_state = 0; in qla82xx_chip_reset_cleanup()
3610 for (i = 0; i < 2; i++) { in qla82xx_chip_reset_cleanup()
3623 ql_dbg(ql_dbg_init, vha, 0x00b0, in qla82xx_chip_reset_cleanup()
3634 for (que = 0; que < ha->max_req_queues; que++) { in qla82xx_chip_reset_cleanup()
3649 0x00b1, in qla82xx_chip_reset_cleanup()
3653 0x00b2, in qla82xx_chip_reset_cleanup()
3664 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, in qla82xx_chip_reset_cleanup()
3666 ql_dbg(ql_dbg_init, vha, 0x00b3, in qla82xx_chip_reset_cleanup()
3693 for (i = 0; i < crb_entry->op_count; i++) { in qla82xx_minidump_process_control()
3702 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3708 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3719 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3728 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3740 crb_addr, 0, 0); in qla82xx_minidump_process_control()
3752 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_control()
3807 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdocm()
3831 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdmux()
3833 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdmux()
3855 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdcrb()
3856 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdcrb()
3889 for (i = 0; i < loop_count; i++) { in qla82xx_minidump_process_l2tag()
3897 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); in qla82xx_minidump_process_l2tag()
3898 if ((c_value_r & p_mask) == 0) in qla82xx_minidump_process_l2tag()
3902 ql_dbg(ql_dbg_p3p, vha, 0xb032, in qla82xx_minidump_process_l2tag()
3903 "c_value_r: 0x%x, poll_mask: 0x%lx, " in qla82xx_minidump_process_l2tag()
3904 "w_time: 0x%lx\n", in qla82xx_minidump_process_l2tag()
3912 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_l2tag()
3913 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l2tag()
3944 for (i = 0; i < loop_count; i++) { in qla82xx_minidump_process_l1cache()
3948 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_l1cache()
3949 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l1cache()
3964 uint32_t r_stride, r_value, r_cnt, qid = 0; in qla82xx_minidump_process_queue()
3975 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_queue()
3978 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_queue()
3979 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_queue()
4002 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdrom()
4004 (r_addr & 0xFFFF0000), 1); in qla82xx_minidump_process_rdrom()
4007 (r_addr & 0x0000FFFF), 0, 0); in qla82xx_minidump_process_rdrom()
4030 if (r_addr & 0xf) { in qla82xx_minidump_process_rdmem()
4031 ql_log(ql_log_warn, vha, 0xb033, in qla82xx_minidump_process_rdmem()
4032 "Read addr 0x%x not 16 bytes aligned\n", r_addr); in qla82xx_minidump_process_rdmem()
4037 ql_log(ql_log_warn, vha, 0xb034, in qla82xx_minidump_process_rdmem()
4038 "Read data[0x%x] not multiple of 16 bytes\n", in qla82xx_minidump_process_rdmem()
4043 ql_dbg(ql_dbg_p3p, vha, 0xb035, in qla82xx_minidump_process_rdmem()
4044 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", in qla82xx_minidump_process_rdmem()
4048 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdmem()
4050 r_value = 0; in qla82xx_minidump_process_rdmem()
4057 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_minidump_process_rdmem()
4059 MD_MIU_TEST_AGT_CTRL, 0, 0); in qla82xx_minidump_process_rdmem()
4060 if ((r_value & MIU_TA_CTL_BUSY) == 0) in qla82xx_minidump_process_rdmem()
4071 for (j = 0; j < 4; j++) { in qla82xx_minidump_process_rdmem()
4073 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); in qla82xx_minidump_process_rdmem()
4087 uint64_t chksum = 0; in qla82xx_validate_template_chksum()
4091 while (count-- > 0) in qla82xx_validate_template_chksum()
4094 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); in qla82xx_validate_template_chksum()
4103 ql_dbg(ql_dbg_p3p, vha, 0xb036, in qla82xx_mark_entry_skipped()
4105 "ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla82xx_mark_entry_skipped()
4114 int no_entry_hdr = 0; in qla82xx_md_collect()
4118 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; in qla82xx_md_collect()
4119 int i = 0, rval = QLA_FUNCTION_FAILED; in qla82xx_md_collect()
4125 ql_log(ql_log_warn, vha, 0xb037, in qla82xx_md_collect()
4134 ql_log(ql_log_warn, vha, 0xb038, in qla82xx_md_collect()
4140 ql_log(ql_log_warn, vha, 0xb054, in qla82xx_md_collect()
4143 ha->flags.isp82xx_no_md_cap = 0; in qla82xx_md_collect()
4148 ql_log(ql_log_info, vha, 0xb039, in qla82xx_md_collect()
4154 ql_dbg(ql_dbg_p3p, vha, 0xb03a, in qla82xx_md_collect()
4155 "No of entry headers in Template: 0x%x\n", no_entry_hdr); in qla82xx_md_collect()
4157 ql_dbg(ql_dbg_p3p, vha, 0xb03b, in qla82xx_md_collect()
4158 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); in qla82xx_md_collect()
4160 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; in qla82xx_md_collect()
4163 if ((f_capture_mask & 0x3) != 0x3) { in qla82xx_md_collect()
4164 ql_log(ql_log_warn, vha, 0xb03c, in qla82xx_md_collect()
4165 "Minimum required capture mask[0x%x] level not set\n", in qla82xx_md_collect()
4171 tmplt_hdr->driver_info[0] = vha->host_no; in qla82xx_md_collect()
4178 ql_dbg(ql_dbg_p3p, vha, 0xb03d, in qla82xx_md_collect()
4179 "Total minidump data_size 0x%x to be captured\n", total_data_size); in qla82xx_md_collect()
4183 ql_log(ql_log_warn, vha, 0xb04e, in qla82xx_md_collect()
4184 "Bad template header entry type: 0x%x obtained\n", in qla82xx_md_collect()
4193 for (i = 0; i < no_entry_hdr; i++) { in qla82xx_md_collect()
4196 ql_log(ql_log_warn, vha, 0xb03e, in qla82xx_md_collect()
4197 "More MiniDump data collected: [0x%x]\n", in qla82xx_md_collect()
4206 ql_dbg(ql_dbg_p3p, vha, 0xb03f, in qla82xx_md_collect()
4208 "ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla82xx_md_collect()
4214 ql_dbg(ql_dbg_p3p, vha, 0xb040, in qla82xx_md_collect()
4216 "entry_type: 0x%x, capture_mask: 0x%x\n", in qla82xx_md_collect()
4221 ql_dbg(ql_dbg_p3p, vha, 0xb041, in qla82xx_md_collect()
4222 "Data collected: [0x%x], Dump size left:[0x%x]\n", in qla82xx_md_collect()
4290 ql_dbg(ql_dbg_p3p, vha, 0xb042, in qla82xx_md_collect()
4301 ql_dbg(ql_dbg_p3p, vha, 0xb043, in qla82xx_md_collect()
4302 "MiniDump data mismatch: Data collected: [0x%x]," in qla82xx_md_collect()
4303 "total_data_size:[0x%x]\n", in qla82xx_md_collect()
4308 ql_log(ql_log_info, vha, 0xb044, in qla82xx_md_collect()
4327 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { in qla82xx_md_alloc()
4328 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; in qla82xx_md_alloc()
4329 ql_log(ql_log_info, vha, 0xb045, in qla82xx_md_alloc()
4330 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", in qla82xx_md_alloc()
4334 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { in qla82xx_md_alloc()
4340 ql_log(ql_log_warn, vha, 0xb046, in qla82xx_md_alloc()
4347 ql_log(ql_log_warn, vha, 0xb047, in qla82xx_md_alloc()
4349 "(0x%x).\n", ha->md_dump_size); in qla82xx_md_alloc()
4352 return 0; in qla82xx_md_alloc()
4362 ql_log(ql_log_info, vha, 0xb048, in qla82xx_md_free()
4372 ql_log(ql_log_info, vha, 0xb049, in qla82xx_md_free()
4376 ha->md_dump_size = 0; in qla82xx_md_free()
4390 ql_log(ql_log_info, vha, 0xb04a, in qla82xx_md_prep()
4401 ql_dbg(ql_dbg_p3p, vha, 0xb04b, in qla82xx_md_prep()
4407 ql_log(ql_log_info, vha, 0xb04c, in qla82xx_md_prep()
4411 ql_log(ql_log_info, vha, 0xb04d, in qla82xx_md_prep()
4436 ql_log(ql_log_warn, vha, 0xb050, in qla82xx_beacon_on()
4454 rval = qla82xx_mbx_beacon_ctl(vha, 0); in qla82xx_beacon_off()
4457 ql_log(ql_log_warn, vha, 0xb051, in qla82xx_beacon_off()
4461 ha->beacon_blink_led = 0; in qla82xx_beacon_off()