Searched +full:0 +full:x12200000 (Results 1 – 6 of 6) sorted by relevance
51 reg = <0x12200000 0x1000>;52 interrupts = <0 75 0>;61 #size-cells = <0>;69 data-addr = <0x200>;70 fifo-depth = <0x80>;
28 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.49 - valid value for tx phase shift and rx phase shift is 0 to 7.52 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx53 phase shift clocks should be 0.74 reg = <0x12200000 0x1000>;75 interrupts = <0 75 0>;77 #size-cells = <0>;84 fifo-depth = <0x80>;89 samsung,dw-mshc-hs400-timing = <0 2>;
31 #size-cells = <0>;33 cpu0: cpu@0 {36 reg = <0x0>;43 reg = <0x1>;50 reg = <0x2>;57 reg = <0x3>;70 reg = <0x10040000 0x5000>;78 reg = <0x10010000 0x30000>;84 reg = <0x03810000 0x0C>;92 reg = <0x10060000 0x100>;[all …]
18 #size-cells = <0>;20 cpu@0 {24 reg = <0>;44 reg = <0x0 0x0>;49 interrupts = <1 9 0x304>;55 #clock-cells = <0>;61 #clock-cells = <0>;67 #clock-cells = <0>;79 io-channels = <&xoadc 0x00 0x01>, /* Battery */80 <&xoadc 0x00 0x02>, /* DC in (charger) */[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0>;169 reg = <0x02020000 0x30000>;172 ranges = <0 0x02020000 0x30000>;174 smp-sram@0 {176 reg = <0x0 0x1000>;181 reg = <0x2f000 0x1000>;187 reg = <0x10044000 0x20>;188 #power-domain-cells = <0>;[all …]
162 reg = <0x10d20000 0x1000>;163 ranges = <0x0 0x10d20000 0x6000>;168 reg = <0x4000 0x1000>;173 reg = <0x5000 0x1000>;179 reg = <0x10010000 0x30000>;185 reg = <0x03810000 0x0C>;195 reg = <0x11000000 0x10000>;208 #size-cells = <0>;209 reg = <0x12200000 0x2000>;212 fifo-depth = <0x40>;[all …]
