Searched +full:0 +full:x100400 (Results 1 – 5 of 5) sorted by relevance
112 reg = <0xf0000 0x1000>;114 #size-cells = <0>;121 reg = <0x1120000 0x1000>;123 #size-cells = <0>;133 reg = <0x2000 0x100>;135 #size-cells = <0>;138 interrupts = <0>;142 reg = <0x64>;148 reg = <0x100400 0x100>, <0x198 0x8>;149 pinctrl-0 = <&i2c_pins>;[all …]
22 #define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x10010024 #define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x10010426 #define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x10010828 #define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C30 #define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x10011032 #define mmMME4_RTR_HBW_E_ARB_MAX 0x10012034 #define mmMME4_RTR_HBW_W_ARB_MAX 0x10012436 #define mmMME4_RTR_HBW_N_ARB_MAX 0x10012838 #define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C40 #define mmMME4_RTR_HBW_L_ARB_MAX 0x100130[all …]
11 #size-cells = <0>;13 cpu@0 {17 reg = <0>;26 #address-cells = <0>;34 #clock-cells = <0>;40 #clock-cells = <0>;50 ranges = <0 0x70000000 0x2000000>;54 cpu_ctrl: syscon@0 {56 reg = <0x0 0x2c>;61 reg = <0x70 0x70>;[all …]
10 #define DSPXRAM_START 0x00000011 #define DSPXRAM_END 0x013FFC12 #define DSPAXRAM_START 0x02000013 #define DSPAXRAM_END 0x023FFC14 #define DSPYRAM_START 0x04000015 #define DSPYRAM_END 0x04FFFC16 #define DSPAYRAM_START 0x02000017 #define DSPAYRAM_END 0x063FFC18 #define DSPMICRO_START 0x08000019 #define DSPMICRO_END 0x0B3FFC[all …]
25 #define FZA_REG_BASE 0x100000 /* register base address */26 #define FZA_REG_RESET 0x100200 /* reset, r/w */27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */28 #define FZA_REG_STATUS 0x100402 /* status, r/o */29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */[all …]
