Lines Matching +full:0 +full:x100400
25 #define FZA_REG_BASE 0x100000 /* register base address */
26 #define FZA_REG_RESET 0x100200 /* reset, r/w */
27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28 #define FZA_REG_STATUS 0x100402 /* status, r/o */
29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
39 #define FZA_EVENT_DLU_DONE 0x0800 /* flash memory write complete */
40 #define FZA_EVENT_FLUSH_TX 0x0400 /* transmit ring flush request */
41 #define FZA_EVENT_PM_PARITY_ERR 0x0200 /* onboard packet memory parity err */
42 #define FZA_EVENT_HB_PARITY_ERR 0x0100 /* host bus parity error */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
47 #define FZA_EVENT_LINK_ST_CHG 0x0040 /* link status change */
48 #define FZA_EVENT_STATE_CHG 0x0020 /* adapter state change */
49 #define FZA_EVENT_UNS_POLL 0x0010 /* unsolicited event service request */
50 #define FZA_EVENT_CMD_DONE 0x0008 /* command done ack */
51 #define FZA_EVENT_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
52 #define FZA_EVENT_RX_POLL 0x0002 /* receive request (packet avail.) */
53 #define FZA_EVENT_TX_DONE 0x0001 /* RMC transmit done ack */
56 #define FZA_STATUS_DLU_SHIFT 0xc /* down line upgrade status bits */
57 #define FZA_STATUS_DLU_MASK 0x03
58 #define FZA_STATUS_LINK_SHIFT 0xb /* link status bits */
59 #define FZA_STATUS_LINK_MASK 0x01
60 #define FZA_STATUS_STATE_SHIFT 0x8 /* adapter state bits */
61 #define FZA_STATUS_STATE_MASK 0x07
62 #define FZA_STATUS_HALT_SHIFT 0x0 /* halt reason bits */
63 #define FZA_STATUS_HALT_MASK 0xff
64 #define FZA_STATUS_TEST_SHIFT 0x0 /* test failure bits */
65 #define FZA_STATUS_TEST_MASK 0xff
78 #define FZA_DLU_FAILURE 0x0 /* DLU catastrophic error; brain dead */
79 #define FZA_DLU_ERROR 0x1 /* DLU error; old firmware intact */
80 #define FZA_DLU_SUCCESS 0x2 /* DLU OK; new firmware loaded */
82 #define FZA_LINK_OFF 0x0 /* link unavailable */
83 #define FZA_LINK_ON 0x1 /* link available */
85 #define FZA_STATE_RESET 0x0 /* resetting */
86 #define FZA_STATE_UNINITIALIZED 0x1 /* after a reset */
87 #define FZA_STATE_INITIALIZED 0x2 /* initialized */
88 #define FZA_STATE_RUNNING 0x3 /* running (link active) */
89 #define FZA_STATE_MAINTENANCE 0x4 /* running (link looped back) */
90 #define FZA_STATE_HALTED 0x5 /* halted (error condition) */
92 #define FZA_HALT_UNKNOWN 0x00 /* unknown reason */
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
94 #define FZA_HALT_HB_PARITY 0x02 /* host bus parity error */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
96 #define FZA_HALT_SW 0x04 /* adapter software fault */
97 #define FZA_HALT_HW 0x05 /* adapter hardware fault */
98 #define FZA_HALT_PC_TRACE 0x06 /* PC Trace path test */
99 #define FZA_HALT_DLSW 0x07 /* data link software fault */
100 #define FZA_HALT_DLHW 0x08 /* data link hardware fault */
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
103 #define FZA_TEST_68K 0x01 /* 68000 CPU */
104 #define FZA_TEST_SRAM_BWADDR 0x02 /* SRAM byte/word address */
105 #define FZA_TEST_SRAM_DBUS 0x03 /* SRAM data bus */
106 #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107 #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
108 #define FZA_TEST_SRAM_COUPL1 0x06 /* SRAM coupling range 1 */
109 #define FZA_TEST_SRAM_COUPL2 0x07 /* SRAM coupling */
110 #define FZA_TEST_FLASH_CRC 0x08 /* Flash CRC */
111 #define FZA_TEST_ROM 0x09 /* option ROM */
112 #define FZA_TEST_PHY_CSR 0x0a /* PHY CSR */
113 #define FZA_TEST_MAC_BIST 0x0b /* MAC BiST */
114 #define FZA_TEST_MAC_CSR 0x0c /* MAC CSR */
115 #define FZA_TEST_MAC_ADDR_UNIQ 0x0d /* MAC unique address */
116 #define FZA_TEST_ELM_BIST 0x0e /* ELM BiST */
117 #define FZA_TEST_ELM_CSR 0x0f /* ELM CSR */
118 #define FZA_TEST_ELM_ADDR_UNIQ 0x10 /* ELM unique address */
119 #define FZA_TEST_CAM 0x11 /* CAM */
120 #define FZA_TEST_NIROM 0x12 /* NI ROM checksum */
121 #define FZA_TEST_SC_LOOP 0x13 /* SC loopback packet */
122 #define FZA_TEST_LM_LOOP 0x14 /* LM loopback packet */
123 #define FZA_TEST_EB_LOOP 0x15 /* EB loopback packet */
124 #define FZA_TEST_SC_LOOP_BYPS 0x16 /* SC bypass loopback packet */
125 #define FZA_TEST_LM_LOOP_LOCAL 0x17 /* LM local loopback packet */
126 #define FZA_TEST_EB_LOOP_LOCAL 0x18 /* EB local loopback packet */
127 #define FZA_TEST_CDC_LOOP 0x19 /* CDC loopback packet */
128 #define FZA_TEST_FIBER_LOOP 0x1A /* FIBER loopback packet */
129 #define FZA_TEST_CAM_MATCH_LOOP 0x1B /* CAM match packet loopback */
130 #define FZA_TEST_68K_IRQ_STUCK 0x1C /* 68000 interrupt line stuck-at */
131 #define FZA_TEST_IRQ_PRESENT 0x1D /* interrupt present register */
132 #define FZA_TEST_RMC_BIST 0x1E /* RMC BiST */
133 #define FZA_TEST_RMC_CSR 0x1F /* RMC CSR */
134 #define FZA_TEST_RMC_ADDR_UNIQ 0x20 /* RMC unique address */
135 #define FZA_TEST_PM_DPATH 0x21 /* packet memory data path */
136 #define FZA_TEST_PM_ADDR 0x22 /* packet memory address */
137 #define FZA_TEST_RES_23 0x23 /* reserved */
138 #define FZA_TEST_PM_DESC 0x24 /* packet memory descriptor */
139 #define FZA_TEST_PM_OWN 0x25 /* packet memory own bit */
140 #define FZA_TEST_PM_PARITY 0x26 /* packet memory parity */
141 #define FZA_TEST_PM_BSWAP 0x27 /* packet memory byte swap */
142 #define FZA_TEST_PM_WSWAP 0x28 /* packet memory word swap */
143 #define FZA_TEST_PM_REF 0x29 /* packet memory refresh */
144 #define FZA_TEST_PM_CSR 0x2A /* PM CSR */
145 #define FZA_TEST_PORT_STATUS 0x2B /* port status register */
146 #define FZA_TEST_HOST_IRQMASK 0x2C /* host interrupt mask */
147 #define FZA_TEST_TIMER_IRQ1 0x2D /* RTOS timer */
148 #define FZA_TEST_FORCE_IRQ1 0x2E /* force RTOS IRQ1 */
149 #define FZA_TEST_TIMER_IRQ5 0x2F /* IRQ5 backoff timer */
150 #define FZA_TEST_FORCE_IRQ5 0x30 /* force IRQ5 */
151 #define FZA_TEST_RES_31 0x31 /* reserved */
152 #define FZA_TEST_IC_PRIO 0x32 /* interrupt controller priority */
153 #define FZA_TEST_PM_FULL 0x33 /* full packet memory */
154 #define FZA_TEST_PMI_DMA 0x34 /* PMI DMA */
157 #define FZA_MASK_RESERVED 0xf000 /* unused */
158 #define FZA_MASK_DLU_DONE 0x0800 /* flash memory write complete */
159 #define FZA_MASK_FLUSH_TX 0x0400 /* transmit ring flush request */
160 #define FZA_MASK_PM_PARITY_ERR 0x0200 /* onboard packet memory parity error
162 #define FZA_MASK_HB_PARITY_ERR 0x0100 /* host bus parity error */
163 #define FZA_MASK_NXM_ERR 0x0080 /* adapter non-existent memory
166 #define FZA_MASK_LINK_ST_CHG 0x0040 /* link status change */
167 #define FZA_MASK_STATE_CHG 0x0020 /* adapter state change */
168 #define FZA_MASK_UNS_POLL 0x0010 /* unsolicited event service request */
169 #define FZA_MASK_CMD_DONE 0x0008 /* command ring entry processed */
170 #define FZA_MASK_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
171 #define FZA_MASK_RCV_POLL 0x0002 /* receive request (packet available)
173 #define FZA_MASK_TX_DONE 0x0001 /* RMC transmit done acknowledge */
175 /* Which interrupts to receive: 0/1 is mask/unmask. */
176 #define FZA_MASK_NONE 0x0000
180 FZA_MASK_NXM_ERR)) & 0xffff)
183 #define FZA_CONTROL_A_HB_PARITY_ERR 0x8000 /* host bus parity error */
184 #define FZA_CONTROL_A_NXM_ERR 0x4000 /* adapter non-existent memory
187 #define FZA_CONTROL_A_SMT_RX_OVFL 0x0040 /* SMT receive overflow */
188 #define FZA_CONTROL_A_FLUSH_DONE 0x0020 /* flush tx request complete */
189 #define FZA_CONTROL_A_SHUT 0x0010 /* turn the interface off */
190 #define FZA_CONTROL_A_HALT 0x0008 /* halt the controller */
191 #define FZA_CONTROL_A_CMD_POLL 0x0004 /* command ring poll */
192 #define FZA_CONTROL_A_SMT_RX_POLL 0x0002 /* SMT receive ring poll */
193 #define FZA_CONTROL_A_TX_POLL 0x0001 /* transmit poll */
198 * 0x0000 after booting into REX,
199 * 0x0003 after issuing `boot #/mop'.
201 #define FZA_CONTROL_B_CONSOLE 0x0002 /* OR with DRIVER for console
204 #define FZA_CONTROL_B_DRIVER 0x0001 /* driver mode */
205 #define FZA_CONTROL_B_IDLE 0x0000 /* no driver installed */
229 u32 cmd_own; /* bit 31: ownership, bits [30:0]: command */
235 #define FZA_RING_CMD 0x200400 /* command ring address */
236 #define FZA_RING_CMD_SIZE 0x40 /* command descriptor ring
240 #define FZA_RING_CMD_MASK 0x7fffffff
241 #define FZA_RING_CMD_NOP 0x00000000 /* nop */
242 #define FZA_RING_CMD_INIT 0x00000001 /* initialize */
243 #define FZA_RING_CMD_MODCAM 0x00000002 /* modify CAM */
244 #define FZA_RING_CMD_PARAM 0x00000003 /* set system parameters */
245 #define FZA_RING_CMD_MODPROM 0x00000004 /* modify promiscuous mode */
246 #define FZA_RING_CMD_SETCHAR 0x00000005 /* set link characteristics */
247 #define FZA_RING_CMD_RDCNTR 0x00000006 /* read counters */
248 #define FZA_RING_CMD_STATUS 0x00000007 /* get link status */
249 #define FZA_RING_CMD_RDCAM 0x00000008 /* read CAM */
252 #define FZA_RING_STAT_SUCCESS 0x00000000
256 u32 own; /* bit 31: ownership, bits [30:0]: reserved */
262 #define FZA_RING_UNS 0x200800 /* unsolicited ring address */
263 #define FZA_RING_UNS_SIZE 0x40 /* unsolicited descriptor ring
267 #define FZA_RING_UNS_UND 0x00000000 /* undefined event ID */
268 #define FZA_RING_UNS_INIT_IN 0x00000001 /* ring init initiated */
269 #define FZA_RING_UNS_INIT_RX 0x00000002 /* ring init received */
270 #define FZA_RING_UNS_BEAC_IN 0x00000003 /* ring beaconing initiated */
271 #define FZA_RING_UNS_DUP_ADDR 0x00000004 /* duplicate address detected */
272 #define FZA_RING_UNS_DUP_TOK 0x00000005 /* duplicate token detected */
273 #define FZA_RING_UNS_PURG_ERR 0x00000006 /* ring purger error */
274 #define FZA_RING_UNS_STRIP_ERR 0x00000007 /* bridge strip error */
275 #define FZA_RING_UNS_OP_OSC 0x00000008 /* ring op oscillation */
276 #define FZA_RING_UNS_BEAC_RX 0x00000009 /* directed beacon received */
277 #define FZA_RING_UNS_PCT_IN 0x0000000a /* PC trace initiated */
278 #define FZA_RING_UNS_PCT_RX 0x0000000b /* PC trace received */
279 #define FZA_RING_UNS_TX_UNDER 0x0000000c /* transmit underrun */
280 #define FZA_RING_UNS_TX_FAIL 0x0000000d /* transmit failure */
281 #define FZA_RING_UNS_RX_OVER 0x0000000e /* receive overrun */
287 u32 own; /* bit 31: ownership, bits [30:0]: reserved */
291 #define FZA_TX_BUFFER_ADDR(x) (0x200000 | (((x) & 0xffff) << 5))
298 #define FZA_RING_TX_SOP 0x80000000 /* start of packet */
299 #define FZA_RING_TX_EOP 0x40000000 /* end of packet */
300 #define FZA_RING_TX_DTP 0x20000000 /* discard this packet */
301 #define FZA_RING_TX_VBC 0x10000000 /* valid buffer byte count */
302 #define FZA_RING_TX_DCC_MASK 0x0f000000 /* DMA completion code */
303 #define FZA_RING_TX_DCC_SUCCESS 0x01000000 /* transmit succeeded */
304 #define FZA_RING_TX_DCC_DTP_SOP 0x02000000 /* DTP set at SOP */
305 #define FZA_RING_TX_DCC_DTP 0x04000000 /* DTP set within packet */
306 #define FZA_RING_TX_DCC_ABORT 0x05000000 /* MAC-requested abort */
307 #define FZA_RING_TX_DCC_PARITY 0x06000000 /* xmit data parity error */
308 #define FZA_RING_TX_DCC_UNDRRUN 0x07000000 /* transmit underrun */
309 #define FZA_RING_TX_XPO_MASK 0x003fe000 /* transmit packet offset */
314 * bits [22:0]: right-shifted address of the
318 * bits [22:0]: right-shifted address of the
328 #define FZA_RING_RX_SOP 0x80000000 /* start of packet */
329 #define FZA_RING_RX_EOP 0x40000000 /* end of packet */
330 #define FZA_RING_RX_FSC_MASK 0x38000000 /* # of frame status bits */
331 #define FZA_RING_RX_FSB_MASK 0x07c00000 /* frame status bits */
332 #define FZA_RING_RX_FSB_ERR 0x04000000 /* error detected */
333 #define FZA_RING_RX_FSB_ADDR 0x02000000 /* address recognized */
334 #define FZA_RING_RX_FSB_COP 0x01000000 /* frame copied */
335 #define FZA_RING_RX_FSB_F0 0x00800000 /* first additional flag */
336 #define FZA_RING_RX_FSB_F1 0x00400000 /* second additional flag */
337 #define FZA_RING_RX_BAD 0x00200000 /* bad packet */
338 #define FZA_RING_RX_CRC 0x00100000 /* CRC error */
339 #define FZA_RING_RX_RRR_MASK 0x000e0000 /* MAC receive status bits */
340 #define FZA_RING_RX_RRR_OK 0x00000000 /* receive OK */
341 #define FZA_RING_RX_RRR_SADDR 0x00020000 /* source address matched */
342 #define FZA_RING_RX_RRR_DADDR 0x00040000 /* dest address not matched */
343 #define FZA_RING_RX_RRR_ABORT 0x00060000 /* RMC abort */
344 #define FZA_RING_RX_RRR_LENGTH 0x00080000 /* invalid length */
345 #define FZA_RING_RX_RRR_FRAG 0x000a0000 /* fragment */
346 #define FZA_RING_RX_RRR_FORMAT 0x000c0000 /* format error */
347 #define FZA_RING_RX_RRR_RESET 0x000e0000 /* MAC reset */
348 #define FZA_RING_RX_DA_MASK 0x00018000 /* daddr match status bits */
349 #define FZA_RING_RX_DA_NONE 0x00000000 /* no match */
350 #define FZA_RING_RX_DA_PROM 0x00008000 /* promiscuous match */
351 #define FZA_RING_RX_DA_CAM 0x00010000 /* CAM entry match */
352 #define FZA_RING_RX_DA_LOCAL 0x00018000 /* link addr or LLC bcast */
353 #define FZA_RING_RX_SA_MASK 0x00006000 /* saddr match status bits */
354 #define FZA_RING_RX_SA_NONE 0x00000000 /* no match */
355 #define FZA_RING_RX_SA_ALIAS 0x00002000 /* alias address match */
356 #define FZA_RING_RX_SA_CAM 0x00004000 /* CAM entry match */
357 #define FZA_RING_RX_SA_LOCAL 0x00006000 /* link address match */
361 u32 own; /* bit 31: ownership, bits [30:0]: unused */
372 #define FZA_RING_OWN_MASK 0x80000000
373 #define FZA_RING_OWN_FZA 0x00000000 /* permit FZA, forbid host */
374 #define FZA_RING_OWN_HOST 0x80000000 /* permit host, forbid FZA */
375 #define FZA_RING_TX_OWN_RMC 0x80000000 /* permit RMC, forbid host */
376 #define FZA_RING_TX_OWN_HOST 0x00000000 /* permit host, forbid RMC */
379 #define FZA_RING_PBC_MASK 0x00001fff /* frame length */
471 #define FZA_PMD_TYPE_MMF 0 /* Multimode fiber */
504 * def: [0,125000000] [80ns]
505 * C03: [0,9999] [ms]
507 u32 ring_purger; /* ring purger enable: 0|1 */
511 #define FZA_LOOP_NORMAL 0
579 /* Packet request header byte #0. */
580 #define FZA_PRH0_FMT_TYPE_MASK 0xc0 /* type of packet, always zero */
581 #define FZA_PRH0_TOK_TYPE_MASK 0x30 /* type of token required
584 #define FZA_PRH0_TKN_TYPE_ANY 0x30 /* use either token type */
585 #define FZA_PRH0_TKN_TYPE_UNR 0x20 /* use an unrestricted token */
586 #define FZA_PRH0_TKN_TYPE_RST 0x10 /* use a restricted token */
587 #define FZA_PRH0_TKN_TYPE_IMM 0x00 /* send immediately, no token required
589 #define FZA_PRH0_FRAME_MASK 0x08 /* type of frame to send */
590 #define FZA_PRH0_FRAME_SYNC 0x08 /* send a synchronous frame */
591 #define FZA_PRH0_FRAME_ASYNC 0x00 /* send an asynchronous frame */
592 #define FZA_PRH0_MODE_MASK 0x04 /* send mode */
593 #define FZA_PRH0_MODE_IMMED 0x04 /* an immediate mode, send regardless
596 #define FZA_PRH0_MODE_NORMAL 0x00 /* a normal mode, send only if ring
599 #define FZA_PRH0_SF_MASK 0x02 /* send frame first */
600 #define FZA_PRH0_SF_FIRST 0x02 /* send this frame first
603 #define FZA_PRH0_SF_NORMAL 0x00 /* treat this frame normally */
604 #define FZA_PRH0_BCN_MASK 0x01 /* beacon frame */
605 #define FZA_PRH0_BCN_BEACON 0x01 /* send the frame only
608 #define FZA_PRH0_BCN_DATA 0x01 /* send the frame only
613 #define FZA_PRH1_SL_MASK 0x40 /* send frame last */
614 #define FZA_PRH1_SL_LAST 0x40 /* send this frame last, releasing
617 #define FZA_PRH1_SL_NORMAL 0x00 /* treat this frame normally */
618 #define FZA_PRH1_CRC_MASK 0x20 /* CRC append */
619 #define FZA_PRH1_CRC_NORMAL 0x20 /* calculate the CRC and append it
622 #define FZA_PRH1_CRC_SKIP 0x00 /* leave the frame as is */
623 #define FZA_PRH1_TKN_SEND_MASK 0x18 /* type of token to send after the
626 #define FZA_PRH1_TKN_SEND_ORIG 0x18 /* send a token of the same type as the
629 #define FZA_PRH1_TKN_SEND_RST 0x10 /* send a restricted token */
630 #define FZA_PRH1_TKN_SEND_UNR 0x08 /* send an unrestricted token */
631 #define FZA_PRH1_TKN_SEND_NONE 0x00 /* send no token */
632 #define FZA_PRH1_EXTRA_FS_MASK 0x07 /* send extra frame status indicators
634 #define FZA_PRH1_EXTRA_FS_ST 0x07 /* TR RR ST II */
635 #define FZA_PRH1_EXTRA_FS_SS 0x06 /* TR RR SS II */
636 #define FZA_PRH1_EXTRA_FS_SR 0x05 /* TR RR SR II */
637 #define FZA_PRH1_EXTRA_FS_NONE1 0x04 /* TR RR II II */
638 #define FZA_PRH1_EXTRA_FS_RT 0x03 /* TR RR RT II */
639 #define FZA_PRH1_EXTRA_FS_RS 0x02 /* TR RR RS II */
640 #define FZA_PRH1_EXTRA_FS_RR 0x01 /* TR RR RR II */
641 #define FZA_PRH1_EXTRA_FS_NONE 0x00 /* TR RR II II */
643 #define FZA_PRH2_NORMAL 0x00 /* always zero */
658 #if ((FZA_RING_TX_MODE) != 0) && ((FZA_RING_TX_MODE) != 1)
659 # error FZA_RING_TX_MODE has to be either 0 or 1