Searched +full:0 +full:x10000 (Results 1 – 25 of 1031) sorted by relevance
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/Linux-v5.4/Documentation/devicetree/bindings/crypto/ |
D | hisilicon,hip07-sec.txt | 9 Region 0 has registers to control the backend processing engines. 16 Interrupt 0 is for the SEC unit error queue. 29 reg = <0x400 0xd0000000 0x0 0x10000 30 0x400 0xd2000000 0x0 0x10000 31 0x400 0xd2010000 0x0 0x10000 32 0x400 0xd2020000 0x0 0x10000 33 0x400 0xd2030000 0x0 0x10000 34 0x400 0xd2040000 0x0 0x10000 35 0x400 0xd2050000 0x0 0x10000 36 0x400 0xd2060000 0x0 0x10000 [all …]
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/Linux-v5.4/arch/arm/boot/dts/ |
D | imx7s.dtsi | 54 #size-cells = <0>; 61 arm,psci-suspend-param = <0x0010000>; 69 cpu0: cpu@0 { 72 reg = <0>; 82 #clock-cells = <0>; 89 #clock-cells = <0>; 98 #phy-cells = <0>; 105 #phy-cells = <0>; 124 #size-cells = <0>; 126 port@0 { [all …]
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D | ls1021a.dtsi | 73 #size-cells = <0>; 78 reg = <0xf00>; 79 clocks = <&clockgen 1 0>; 86 reg = <0xf01>; 87 clocks = <&clockgen 1 0>; 94 reg = <0x0 0x0 0x0 0x0>; 99 #clock-cells = <0>; 122 offset = <0xb0>; 123 mask = <0x02>; 136 reg = <0x0 0x1080000 0x0 0x1000>; [all …]
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D | prima2.dtsi | 16 #size-cells = <0>; 18 cpu@0 { 21 reg = <0x0>; 27 timebase-frequency = <0>; 28 bus-frequency = <0>; 29 clock-frequency = <0>; 51 ranges = <0x40000000 0x40000000 0x80000000>; 55 reg = <0x80040000 0x1000>; 59 arm,filter-ranges = <0 0x40000000>; 66 reg = <0x80020000 0x1000>; [all …]
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D | atlas6.dtsi | 16 #size-cells = <0>; 18 cpu@0 { 19 reg = <0x0>; 25 timebase-frequency = <0>; 26 bus-frequency = <0>; 27 clock-frequency = <0>; 49 ranges = <0x40000000 0x40000000 0x80000000>; 55 reg = <0x80020000 0x1000>; 62 ranges = <0x88000000 0x88000000 0x40000>; 66 reg = <0x88000000 0x1000>; [all …]
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D | picoxcell-pc3x2.dtsi | 12 #address-cells = <0>; 13 #size-cells = <0>; 31 pclk: clock@0 { 43 ranges = <0 0x80000000 0x400000>; 47 reg = <0x30000 0x10000>; 53 reg = <0x40000 0x10000>; 59 reg = <0x50000 0x10000>; 66 reg = <0x60000 0x1000>; 73 reg = <0x64000 0x1000>; 79 reg = <0x80000 0x10000>; [all …]
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D | exynos5260.dtsi | 35 #size-cells = <0>; 37 cpu@0 { 40 reg = <0x0>; 47 reg = <0x1>; 54 reg = <0x100>; 61 reg = <0x101>; 68 reg = <0x102>; 75 reg = <0x103>; 88 reg = <0x10010000 0x10000>; 94 reg = <0x10200000 0x10000>; [all …]
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/Linux-v5.4/drivers/mtd/chips/ |
D | jedec_probe.c | 26 #define AM29DL800BB 0x22CB 27 #define AM29DL800BT 0x224A 29 #define AM29F800BB 0x2258 30 #define AM29F800BT 0x22D6 31 #define AM29LV400BB 0x22BA 32 #define AM29LV400BT 0x22B9 33 #define AM29LV800BB 0x225B 34 #define AM29LV800BT 0x22DA 35 #define AM29LV160DT 0x22C4 36 #define AM29LV160DB 0x2249 [all …]
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/Linux-v5.4/arch/arm64/boot/dts/freescale/ |
D | imx8mm.dtsi | 45 #size-cells = <0>; 52 arm,psci-suspend-param = <0x0010033>; 60 A53_0: cpu@0 { 63 reg = <0x0>; 77 reg = <0x1>; 89 reg = <0x2>; 101 reg = <0x3>; 122 opp-supported-hw = <0xe>, <0x7>; 130 opp-supported-hw = <0xc>, <0x7>; 138 opp-supported-hw = <0x8>, <0x3>; [all …]
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D | imx8mn.dtsi | 44 #size-cells = <0>; 46 A53_0: cpu@0 { 49 reg = <0x0>; 62 reg = <0x1>; 73 reg = <0x2>; 84 reg = <0x3>; 104 opp-supported-hw = <0xb00>, <0x7>; 112 opp-supported-hw = <0x300>, <0x7>; 120 opp-supported-hw = <0x100>, <0x3>; 128 reg = <0x0 0x40000000 0 0x80000000>; [all …]
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D | fsl-ls1028a.dtsi | 22 #size-cells = <0>; 24 cpu0: cpu@0 { 27 reg = <0x0>; 29 clocks = <&clockgen 1 0>; 38 reg = <0x1>; 40 clocks = <&clockgen 1 0>; 61 arm,psci-suspend-param = <0x0>; 70 #clock-cells = <0>; 77 #clock-cells = <0>; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; [all …]
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D | fsl-ls1046a.dtsi | 35 #size-cells = <0>; 37 cpu0: cpu@0 { 40 reg = <0x0>; 41 clocks = <&clockgen 1 0>; 50 reg = <0x1>; 51 clocks = <&clockgen 1 0>; 60 reg = <0x2>; 61 clocks = <&clockgen 1 0>; 70 reg = <0x3>; 71 clocks = <&clockgen 1 0>; [all …]
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D | fsl-ls1012a.dtsi | 29 #size-cells = <0>; 31 cpu0: cpu@0 { 34 reg = <0x0>; 35 clocks = <&clockgen 1 0>; 51 arm,psci-suspend-param = <0x0>; 60 #clock-cells = <0>; 67 #clock-cells = <0>; 82 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 89 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 90 <0x0 0x1402000 0 0x2000>, /* GICC */ [all …]
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D | fsl-ls1043a.dtsi | 34 #size-cells = <0>; 42 cpu0: cpu@0 { 45 reg = <0x0>; 46 clocks = <&clockgen 1 0>; 55 reg = <0x1>; 56 clocks = <&clockgen 1 0>; 65 reg = <0x2>; 66 clocks = <&clockgen 1 0>; 75 reg = <0x3>; 76 clocks = <&clockgen 1 0>; [all …]
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D | imx8mq.dtsi | 43 #clock-cells = <0>; 50 #clock-cells = <0>; 57 #clock-cells = <0>; 64 #clock-cells = <0>; 71 #clock-cells = <0>; 78 #clock-cells = <0>; 85 #clock-cells = <0>; 92 #size-cells = <0>; 94 A53_0: cpu@0 { 97 reg = <0x0>; [all …]
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D | imx8qxp.dtsi | 40 #size-cells = <0>; 43 A35_0: cpu@0 { 46 reg = <0x0 0x0>; 57 reg = <0x0 0x1>; 68 reg = <0x0 0x2>; 79 reg = <0x0 0x3>; 112 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 113 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 125 reg = <0 0x92400000 0 0x2000000>; 145 mboxes = <&lsio_mu1 0 0 [all …]
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D | fsl-lx2160a.dtsi | 10 /memreserve/ 0x80000000 0x00010000; 20 #size-cells = <0>; 23 cpu@0 { 27 reg = <0x0>; 28 clocks = <&clockgen 1 0>; 29 d-cache-size = <0x8000>; 32 i-cache-size = <0xC000>; 43 reg = <0x1>; 44 clocks = <&clockgen 1 0>; 45 d-cache-size = <0x8000>; [all …]
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D | fsl-ls208xa.dtsi | 31 #size-cells = <0>; 36 reg = <0x00000000 0x80000000 0 0x80000000>; 42 #clock-cells = <0>; 49 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 50 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 51 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 52 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 53 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 59 interrupts = <1 9 0x4>; 64 reg = <0x0 0x6020000 0 0x20000>; [all …]
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/Linux-v5.4/arch/arm64/boot/dts/hisilicon/ |
D | hip07.dtsi | 23 #size-cells = <0>; 270 reg = <0x10000>; 273 numa-node-id = <0>; 279 reg = <0x10001>; 282 numa-node-id = <0>; 288 reg = <0x10002>; 291 numa-node-id = <0>; 297 reg = <0x10003>; 300 numa-node-id = <0>; 306 reg = <0x10100>; [all …]
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/Linux-v5.4/arch/arm64/boot/dts/nvidia/ |
D | tegra194.dtsi | 22 ranges = <0x0 0x0 0x0 0x40000000>; 27 reg = <0x2200000 0x10000>, 28 <0x2210000 0x10000>; 44 reg = <0x02490000 0x10000>; 58 snps,burst-map = <0x7>; 72 ranges = <0x02900000 0x02900000 0x200000>; 78 reg = <0x02930000 0x20000>; 80 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 123 reg = <0x02a41000 0x1000>, 124 <0x02a42000 0x2000>; [all …]
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D | tegra186.dtsi | 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 44 reg = <0x0 0x02490000 0x0 0x10000>; 68 snps,burst-map = <0x7>; 82 ranges = <0x02900000 0x0 0x02900000 0x200000>; 87 reg = <0x02930000 0x20000>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 132 reg = <0x02a41000 0x1000>, [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/arm/tegra/ |
D | nvidia,tegra186-pmc.txt | 28 reg = <0 0x0c360000 0 0x10000>, 29 <0 0x0c370000 0 0x10000>, 30 <0 0x0c380000 0 0x10000>, 31 <0 0x0c390000 0 0x10000>; 88 reg = <0 0x0c360000 0 0x10000>, 89 <0 0x0c370000 0 0x10000>, 90 <0 0x0c380000 0 0x10000>, 91 <0 0x0c390000 0 0x10000>; 121 pinctrl-0 = <&sdmmc1_3v3>; 129 pinctrl-0 = <&hdmi_off>;
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/Linux-v5.4/drivers/net/ethernet/qlogic/netxen/ |
D | netxen_nic_hdr.h | 21 NETXEN_HW_H0_CH_HUB_ADR = 0x05, 22 NETXEN_HW_H1_CH_HUB_ADR = 0x0E, 23 NETXEN_HW_H2_CH_HUB_ADR = 0x03, 24 NETXEN_HW_H3_CH_HUB_ADR = 0x01, 25 NETXEN_HW_H4_CH_HUB_ADR = 0x06, 26 NETXEN_HW_H5_CH_HUB_ADR = 0x07, 27 NETXEN_HW_H6_CH_HUB_ADR = 0x08 30 /* Hub 0 */ 32 NETXEN_HW_MN_CRB_AGT_ADR = 0x15, 33 NETXEN_HW_MS_CRB_AGT_ADR = 0x25 [all …]
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/Linux-v5.4/arch/powerpc/boot/dts/fsl/ |
D | p2020ds.dts | 19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 20 0x1 0x0 0x0 0xe0000000 0x08000000 21 0x2 0x0 0x0 0xffa00000 0x00040000 22 0x3 0x0 0x0 0xffdf0000 0x00008000 23 0x4 0x0 0x0 0xffa40000 0x00040000 24 0x5 0x0 0x0 0xffa80000 0x00040000 25 0x6 0x0 0x0 0xffac0000 0x00040000>; 26 reg = <0 0xffe05000 0 0x1000>; 30 ranges = <0x0 0x0 0xffe00000 0x100000>; 34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 [all …]
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/Linux-v5.4/drivers/gpu/drm/msm/disp/mdp4/ |
D | mdp4.xml.h | 50 VG1 = 0, 60 MIXER0 = 0, 66 INTF_LCDC_DTV = 0, 78 FRAME_LINEAR = 0, 84 SCALE_FIR = 0, 90 DMA_P = 0, 95 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001 96 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002 97 #define MDP4_IRQ_DMA_S_DONE 0x00000004 98 #define MDP4_IRQ_DMA_E_DONE 0x00000008 [all …]
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