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/Linux-v5.15/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/ti/
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
113 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8-ss-lsio.dtsi14 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
18 #clock-cells = <0>;
25 #clock-cells = <0>;
31 reg = <0x5d080000 0x10000>;
41 reg = <0x5d090000 0x10000>;
51 reg = <0x5d0a0000 0x10000>;
61 reg = <0x5d0b0000 0x10000>;
71 reg = <0x5d0c0000 0x10000>;
81 reg = <0x5d0d0000 0x10000>;
91 reg = <0x5d0e0000 0x10000>;
[all …]
Dimx8mp.dtsi45 #size-cells = <0>;
47 A53_0: cpu@0 {
50 reg = <0x0>;
61 reg = <0x1>;
72 reg = <0x2>;
83 reg = <0x3>;
98 #clock-cells = <0>;
105 #clock-cells = <0>;
112 #clock-cells = <0>;
119 #clock-cells = <0>;
[all …]
Dimx8mn.dtsi44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xb00>, <0x7>;
133 opp-supported-hw = <0x300>, <0x7>;
141 opp-supported-hw = <0x100>, <0x3>;
[all …]
Dimx8mm.dtsi44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xe>, <0x7>;
133 opp-supported-hw = <0xc>, <0x7>;
141 opp-supported-hw = <0x8>, <0x3>;
[all …]
Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39 reg = <0x1>;
41 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 arm,psci-suspend-param = <0x0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
85 reg = <0x0 0xf1f0000 0x0 0xffff>;
[all …]
Dfsl-ls1046a.dtsi37 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 reg = <0x1>;
53 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 reg = <0x2>;
63 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
72 reg = <0x3>;
73 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dfsl-ls1043a.dtsi36 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0>;
48 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
57 reg = <0x1>;
58 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
67 reg = <0x2>;
68 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
77 reg = <0x3>;
78 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #size-cells = <0>;
98 A53_0: cpu@0 {
101 reg = <0x0>;
[all …]
Dimx8-ss-conn.dtsi14 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
18 #clock-cells = <0>;
25 #clock-cells = <0>;
32 #clock-cells = <0>;
39 reg = <0x5b010000 0x10000>;
50 reg = <0x5b020000 0x10000>;
63 reg = <0x5b030000 0x10000>;
73 reg = <0x5b040000 0x10000>;
93 reg = <0x5b050000 0x10000>;
115 reg = <0x5b200000 0x10000>;
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx7s.dtsi56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
84 #clock-cells = <0>;
91 #clock-cells = <0>;
100 #phy-cells = <0>;
107 #phy-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
[all …]
Dls1021a.dtsi74 #size-cells = <0>;
79 reg = <0xf00>;
80 clocks = <&clockgen 1 0>;
87 reg = <0xf01>;
88 clocks = <&clockgen 1 0>;
95 reg = <0x0 0x0 0x0 0x0>;
100 #clock-cells = <0>;
123 offset = <0xb0>;
124 mask = <0x02>;
137 reg = <0x0 0x1080000 0x0 0x1000>;
[all …]
Dexynos5260.dtsi35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
120 reg = <0x10200000 0x10000>;
[all …]
/Linux-v5.15/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/Linux-v5.15/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c59 #define RLCG_VFGATE_DISABLED 0x4000000
60 #define RLCG_WRONG_OPERATION_TYPE 0x2000000
61 #define RLCG_NOT_IN_RANGE 0x1000000
64 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
66 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
68 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
70 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
73 …R_CONFIG__NUM_PKRS__SHIFT 0x8
74 …__NUM_PKRS_MASK 0x00000700L
76 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.txt29 reg = <0 0x0c360000 0 0x10000>,
30 <0 0x0c370000 0 0x10000>,
31 <0 0x0c380000 0 0x10000>,
32 <0 0x0c390000 0 0x10000>;
89 reg = <0 0x0c360000 0 0x10000>,
90 <0 0x0c370000 0 0x10000>,
91 <0 0x0c380000 0 0x10000>,
92 <0 0x0c390000 0 0x10000>;
122 pinctrl-0 = <&sdmmc1_3v3>;
130 pinctrl-0 = <&hdmi_off>;
/Linux-v5.15/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic_hdr.h21 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
22 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
23 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
24 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
25 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
26 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
27 NETXEN_HW_H6_CH_HUB_ADR = 0x08
30 /* Hub 0 */
32 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
33 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi14 bus@0 {
19 ranges = <0x0 0x0 0x0 0x40000000>;
23 reg = <0x00100000 0xf000>,
24 <0x0010f000 0x1000>;
30 reg = <0x03100000 0x10000>;
41 reg = <0x03460000 0x20000>;
53 reg = <0x03810000 0x10000>;
60 reg = <0x03c00000 0xa0000>;
78 reg = <0x0c150000 0x90000>;
84 * Shared interrupt 0 is routed only to AON/SPE, so
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h58 VG1 = 0,
68 MIXER0 = 0,
74 INTF_LCDC_DTV = 0,
86 FRAME_LINEAR = 0,
92 SCALE_FIR = 0,
98 DMA_P = 0,
103 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
104 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
105 #define MDP4_IRQ_DMA_S_DONE 0x00000004
106 #define MDP4_IRQ_DMA_E_DONE 0x00000008
[all …]
/Linux-v5.15/drivers/mtd/devices/
Dspear_smi.c51 #define SMI_CR1 0x0 /* SMI control register 1 */
52 #define SMI_CR2 0x4 /* SMI control register 2 */
53 #define SMI_SR 0x8 /* SMI status register */
54 #define SMI_TR 0xC /* SMI transmit register */
55 #define SMI_RR 0x10 /* SMI receive register */
58 #define BANK_EN (0xF << 0) /* enables all banks */
59 #define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */
60 #define SW_MODE (0x1 << 28) /* enables SW Mode */
61 #define WB_MODE (0x1 << 29) /* Write Burst Mode */
62 #define FAST_MODE (0x1 << 15) /* Fast Mode */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt52 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
71 reg = <0x11800 0x00000000 0x0 0x200>;
76 ranges = <0 0 0x0 0x1f400000 0xc00000>,
77 <1 0 0x10000 0x30000000 0>,
78 <2 0 0x10000 0x40000000 0>,
79 <3 0 0x10000 0x50000000 0>,
80 <4 0 0x0 0x1d020000 0x10000>,
81 <5 0 0x0 0x1d040000 0x10000>,
82 <6 0 0x0 0x1d050000 0x10000>,
83 <7 0 0x10000 0x90000000 0>;
[all …]

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