Lines Matching +full:0 +full:x10000
58 VG1 = 0,
68 MIXER0 = 0,
74 INTF_LCDC_DTV = 0,
86 FRAME_LINEAR = 0,
92 SCALE_FIR = 0,
98 DMA_P = 0,
103 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
104 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
105 #define MDP4_IRQ_DMA_S_DONE 0x00000004
106 #define MDP4_IRQ_DMA_E_DONE 0x00000008
107 #define MDP4_IRQ_DMA_P_DONE 0x00000010
108 #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
109 #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
110 #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
111 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
112 #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
113 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
114 #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
115 #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
116 #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
117 #define MDP4_IRQ_OVERLAY2_DONE 0x40000000
118 #define REG_MDP4_VERSION 0x00000000
119 #define MDP4_VERSION_MINOR__MASK 0x00ff0000
125 #define MDP4_VERSION_MAJOR__MASK 0xff000000
132 #define REG_MDP4_OVLP0_KICK 0x00000004
134 #define REG_MDP4_OVLP1_KICK 0x00000008
136 #define REG_MDP4_OVLP2_KICK 0x000000d0
138 #define REG_MDP4_DMA_P_KICK 0x0000000c
140 #define REG_MDP4_DMA_S_KICK 0x00000010
142 #define REG_MDP4_DMA_E_KICK 0x00000014
144 #define REG_MDP4_DISP_STATUS 0x00000018
146 #define REG_MDP4_DISP_INTF_SEL 0x00000038
147 #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
148 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
153 #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
159 #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
165 #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
166 #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
168 #define REG_MDP4_RESET_STATUS 0x0000003c
170 #define REG_MDP4_READ_CNFG 0x0000004c
172 #define REG_MDP4_INTR_ENABLE 0x00000050
174 #define REG_MDP4_INTR_STATUS 0x00000054
176 #define REG_MDP4_INTR_CLEAR 0x00000058
178 #define REG_MDP4_EBI2_LCD0 0x00000060
180 #define REG_MDP4_EBI2_LCD1 0x00000064
182 #define REG_MDP4_PORTMAP_MODE 0x00000070
184 #define REG_MDP4_CS_CONTROLLER0 0x000000c0
186 #define REG_MDP4_CS_CONTROLLER1 0x000000c4
188 #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
189 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
190 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
196 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
203 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
210 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
217 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
224 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
231 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
237 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
238 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
244 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
246 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
248 #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
249 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
250 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
255 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
256 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
262 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
263 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
269 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
270 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
276 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
277 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
283 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
284 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
290 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
291 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
297 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
298 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
304 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
306 #define REG_MDP4_VG2_SRC_FORMAT 0x00030050
308 #define REG_MDP4_VG2_CONST_COLOR 0x00031008
310 #define REG_MDP4_OVERLAY_FLUSH 0x00018000
311 #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
312 #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
313 #define MDP4_OVERLAY_FLUSH_VG1 0x00000004
314 #define MDP4_OVERLAY_FLUSH_VG2 0x00000008
315 #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
316 #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
321 case 0: return 0x00010000; in __offset_OVLP()
322 case 1: return 0x00018000; in __offset_OVLP()
323 case 2: return 0x00088000; in __offset_OVLP()
327 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP()
329 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG()
331 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE()
332 #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
338 #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
339 #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
345 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE()
347 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE()
349 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE()
354 case 0: return 0x00000104; in __offset_STAGE()
355 case 1: return 0x00000124; in __offset_STAGE()
356 case 2: return 0x00000144; in __offset_STAGE()
357 case 3: return 0x00000160; in __offset_STAGE()
361 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset… in REG_MDP4_OVLP_STAGE()
363 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP4_OVLP_STAGE_OP()
364 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
365 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
370 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
371 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
372 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
378 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
379 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
380 #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
381 #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
383 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +… in REG_MDP4_OVLP_STAGE_FG_ALPHA()
385 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +… in REG_MDP4_OVLP_STAGE_BG_ALPHA()
387 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000… in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
389 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x0000001… in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
391 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
393 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()
398 case 0: return 0x00001004; in __offset_STAGE_CO3()
399 case 1: return 0x00001404; in __offset_STAGE_CO3()
400 case 2: return 0x00001804; in __offset_STAGE_CO3()
401 case 3: return 0x00001b84; in __offset_STAGE_CO3()
405 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __of… in REG_MDP4_OVLP_STAGE_CO3()
407 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + … in REG_MDP4_OVLP_STAGE_CO3_SEL()
408 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
410 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i… in REG_MDP4_OVLP_TRANSP_LOW0()
412 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i… in REG_MDP4_OVLP_TRANSP_LOW1()
414 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(… in REG_MDP4_OVLP_TRANSP_HIGH0()
416 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(… in REG_MDP4_OVLP_TRANSP_HIGH1()
418 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0… in REG_MDP4_OVLP_CSC_CONFIG()
420 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CSC()
423 …_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_MV()
425 …EG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_MV_VAL()
427 …EG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_BV()
429 …DP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_BV_VAL()
431 …G_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_BV()
433 …P4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_BV_VAL()
435 …EG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_LV()
437 …DP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_LV_VAL()
439 …G_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_LV()
441 …P4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_LV_VAL()
443 #define REG_MDP4_DMA_P_OP_MODE 0x00090070
445 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } in REG_MDP4_LUTN()
447 …ine uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } in REG_MDP4_LUTN_LUT()
449 …uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } in REG_MDP4_LUTN_LUT_VAL()
451 #define REG_MDP4_DMA_S_OP_MODE 0x000a0028
453 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } in REG_MDP4_DMA_E_QUANT()
458 case DMA_P: return 0x00090000; in __offset_DMA()
459 case DMA_S: return 0x000a0000; in __offset_DMA()
460 case DMA_E: return 0x000b0000; in __offset_DMA()
464 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA()
466 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)… in REG_MDP4_DMA_CONFIG()
467 #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
468 #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
473 #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
479 #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
485 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
486 #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
492 #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
493 #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
495 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i… in REG_MDP4_DMA_SRC_SIZE()
496 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
502 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
503 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
509 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i… in REG_MDP4_DMA_SRC_BASE()
511 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA… in REG_MDP4_DMA_SRC_STRIDE()
513 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i… in REG_MDP4_DMA_DST_SIZE()
514 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
520 #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
521 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
527 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM… in REG_MDP4_DMA_CURSOR_SIZE()
528 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
529 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
534 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
541 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM… in REG_MDP4_DMA_CURSOR_BASE()
543 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA… in REG_MDP4_DMA_CURSOR_POS()
544 #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
545 #define MDP4_DMA_CURSOR_POS_X__SHIFT 0
550 #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
557 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o… in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
558 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
559 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
565 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
567 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of… in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
569 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse… in REG_MDP4_DMA_BLEND_TRANS_LOW()
571 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs… in REG_MDP4_DMA_BLEND_TRANS_HIGH()
573 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D… in REG_MDP4_DMA_FETCH_CONFIG()
575 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } in REG_MDP4_DMA_CSC()
578 …REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_MV()
580 …MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_MV_VAL()
582 …MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_BV()
584 …_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_BV_VAL()
586 …DP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_BV()
588 …DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_BV_VAL()
590 …MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_LV()
592 …_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_LV_VAL()
594 …DP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_LV()
596 …DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_LV_VAL()
598 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE()
600 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_SIZE()
601 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
607 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
608 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
614 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_XY()
615 #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
621 #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
622 #define MDP4_PIPE_SRC_XY_X__SHIFT 0
628 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } in REG_MDP4_PIPE_DST_SIZE()
629 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
635 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
636 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
642 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } in REG_MDP4_PIPE_DST_XY()
643 #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
649 #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
650 #define MDP4_PIPE_DST_XY_X__SHIFT 0
656 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0… in REG_MDP4_PIPE_SRCP0_BASE()
658 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0… in REG_MDP4_PIPE_SRCP1_BASE()
660 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0… in REG_MDP4_PIPE_SRCP2_BASE()
662 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0… in REG_MDP4_PIPE_SRCP3_BASE()
664 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*… in REG_MDP4_PIPE_SRC_STRIDE_A()
665 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
666 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
671 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
678 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*… in REG_MDP4_PIPE_SRC_STRIDE_B()
679 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
680 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
685 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
692 …ine uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } in REG_MDP4_PIPE_SSTILE_FRAME_SIZE()
693 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
699 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
700 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
706 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0… in REG_MDP4_PIPE_SRC_FORMAT()
707 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
708 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
713 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
719 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
725 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
731 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
732 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
738 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
739 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
745 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
746 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
747 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
753 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
754 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
760 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
767 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0… in REG_MDP4_PIPE_SRC_UNPACK()
768 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
769 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
774 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
780 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
786 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
793 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } in REG_MDP4_PIPE_OP_MODE()
794 #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
795 #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
796 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
802 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
808 #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
809 #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
810 #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
811 #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
812 #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
813 #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
814 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
815 #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
816 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
818 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i… in REG_MDP4_PIPE_PHASEX_STEP()
820 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i… in REG_MDP4_PIPE_PHASEY_STEP()
822 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*… in REG_MDP4_PIPE_FETCH_CONFIG()
824 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i… in REG_MDP4_PIPE_SOLID_COLOR()
826 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } in REG_MDP4_PIPE_CSC()
829 …t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_MV()
831 …G_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_MV_VAL()
833 …G_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_BV()
835 …P4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
837 …_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_BV()
839 …4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_BV_VAL()
841 …G_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_LV()
843 …P4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
845 …_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_LV()
847 …4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_LV_VAL()
849 #define REG_MDP4_LCDC 0x000c0000
851 #define REG_MDP4_LCDC_ENABLE 0x000c0000
853 #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
854 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
855 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
860 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
867 #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
869 #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
871 #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
872 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
873 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
878 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
885 #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
887 #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
889 #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
890 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
891 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
896 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
902 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
904 #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
906 #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
908 #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
910 #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
911 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
912 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
917 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
919 #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
921 #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
923 #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
924 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
925 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
926 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
928 #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
929 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
930 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
931 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
932 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
933 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
934 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
935 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
936 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
937 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
938 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
939 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
940 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
941 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
942 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
943 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
944 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
946 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } in REG_MDP4_LCDC_LVDS_MUX_CTL()
948 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0()
949 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
950 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
955 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
961 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
967 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
974 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4()
975 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
976 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
981 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
987 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
994 #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
996 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
998 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
1000 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
1002 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
1004 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
1006 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
1008 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
1010 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
1012 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
1014 #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
1016 #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
1018 #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
1019 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
1020 #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
1021 #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
1023 #define REG_MDP4_DTV 0x000d0000
1025 #define REG_MDP4_DTV_ENABLE 0x000d0000
1027 #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
1028 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1029 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
1034 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1041 #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
1043 #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
1045 #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
1046 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
1047 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
1052 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
1059 #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
1061 #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
1063 #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
1064 #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
1065 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
1070 #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
1076 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1078 #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
1080 #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
1082 #define REG_MDP4_DTV_BORDER_CLR 0x000d0040
1084 #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
1085 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1086 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
1091 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1093 #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
1095 #define REG_MDP4_DTV_TEST_CNTL 0x000d004c
1097 #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
1098 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
1099 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
1100 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1102 #define REG_MDP4_DSI 0x000e0000
1104 #define REG_MDP4_DSI_ENABLE 0x000e0000
1106 #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
1107 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1108 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
1113 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1120 #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
1122 #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
1124 #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
1125 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
1126 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
1131 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
1138 #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
1140 #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
1142 #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
1143 #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
1144 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
1149 #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
1155 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1157 #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
1159 #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
1161 #define REG_MDP4_DSI_BORDER_CLR 0x000e0028
1163 #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
1164 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1165 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
1170 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1172 #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
1174 #define REG_MDP4_DSI_TEST_CNTL 0x000e0034
1176 #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
1177 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
1178 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
1179 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004