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/Linux-v6.1/include/linux/bcma/
Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
[all …]
Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
[all …]
/Linux-v6.1/include/linux/ssb/
Dssb_driver_gige.h14 #define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
15 #define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
17 #define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
19 #define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
20 #define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
21 #define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
22 #define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_d.h26 #define ixCLIENT0_BM 0x0220
27 #define ixCLIENT0_CD0 0x0210
28 #define ixCLIENT0_CD1 0x0214
29 #define ixCLIENT0_CD2 0x0218
30 #define ixCLIENT0_CD3 0x021C
31 #define ixCLIENT0_CK0 0x0200
32 #define ixCLIENT0_CK1 0x0204
33 #define ixCLIENT0_CK2 0x0208
34 #define ixCLIENT0_CK3 0x020C
35 #define ixCLIENT0_K0 0x01F0
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Dqcom,sdm845-camss.yaml96 port@0:
321 iommus = <&apps_smmu 0x0808 0x0>,
322 <&apps_smmu 0x0810 0x8>,
323 <&apps_smmu 0x0c08 0x0>,
324 <&apps_smmu 0x0c10 0x8>;
330 reg = <0 0xacb3000 0 0x1000>,
331 <0 0xacba000 0 0x1000>,
332 <0 0xacc8000 0 0x1000>,
333 <0 0xac65000 0 0x1000>,
334 <0 0xac66000 0 0x1000>,
[all …]
/Linux-v6.1/drivers/media/platform/st/sti/bdisp/
Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtw88/
Drtw8723d.h20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 channel_plan; /* 0xb8 */
57 u8 pa_type; /* 0xbc */
58 u8 lna_type_2g[2]; /* 0xbd */
68 u8 rf_antenna_option; /* 0xc9 */
79 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
83 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
85 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
87 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
[all …]
/Linux-v6.1/arch/powerpc/include/asm/
Dcell-regs.h28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
/Linux-v6.1/drivers/media/i2c/s5c73m3/
Ds5c73m3.h44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
/Linux-v6.1/drivers/iommu/
Dfsl_pamu.h22 #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
23 #define PAMU_PE 0x40000000 /* enable PAMU */
26 #define PAMU_OFFSET 0x1000
28 #define PAMU_MMAP_REGS_BASE 0
46 #define PAMU_POES1 0x0040
47 #define PAMU_POES2 0x0044
48 #define PAMU_POEAH 0x0048
49 #define PAMU_POEAL 0x004C
50 #define PAMU_AVS1 0x0050
51 #define PAMU_AVS1_AV 0x1
[all …]
/Linux-v6.1/drivers/video/fbdev/kyro/
DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
/Linux-v6.1/include/linux/mfd/
Dmotorola-cpcap.h17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
/Linux-v6.1/drivers/net/dsa/microchip/
Dksz9477_reg.h11 #define KS_PRIO_M 0x7
14 /* 0 - Operation */
15 #define REG_CHIP_ID0__1 0x0000
17 #define REG_CHIP_ID1__1 0x0001
19 #define FAMILY_ID 0x95
20 #define FAMILY_ID_94 0x94
21 #define FAMILY_ID_95 0x95
22 #define FAMILY_ID_85 0x85
23 #define FAMILY_ID_98 0x98
24 #define FAMILY_ID_88 0x88
[all …]
/Linux-v6.1/drivers/gpu/drm/gma500/
Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/Linux-v6.1/arch/powerpc/platforms/ps3/
Dspu.c36 SPE_TYPE_LOGICAL = 0,
46 u8 padding_0140[0x0140];
47 u64 int_status_class0_RW; /* 0x0140 */
48 u64 int_status_class1_RW; /* 0x0148 */
49 u64 int_status_class2_RW; /* 0x0150 */
50 u8 padding_0158[0x0610-0x0158];
51 u64 mfc_dsisr_RW; /* 0x0610 */
52 u8 padding_0618[0x0620-0x0618];
53 u64 mfc_dar_RW; /* 0x0620 */
54 u8 padding_0628[0x0800-0x0628];
[all …]
/Linux-v6.1/drivers/media/i2c/ccs/
Dsmiapp-reg-defs.h16 #define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
17 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
18 #define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
19 #define SMIAPP_REG_U8_SMIA_VERSION 0x0004
20 #define SMIAPP_REG_U8_FRAME_COUNT 0x0005
21 #define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
22 #define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
23 #define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
24 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
25 #define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
[all …]
/Linux-v6.1/drivers/media/platform/qcom/camss/
Dcamss-csiphy-3ph-1-0.c3 * camss-csiphy-3ph-1-0.c
5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n))
20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n))
22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5
26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
[all …]
/Linux-v6.1/drivers/usb/mtu3/
Dmtu3_hw_regs.h14 #define SSUSB_DEV_BASE 0x0000
15 #define SSUSB_EPCTL_CSR_BASE 0x0800
16 #define SSUSB_USB3_MAC_CSR_BASE 0x1400
17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400
18 #define SSUSB_USB2_CSR_BASE 0x2400
21 #define SSUSB_SIFSLV_IPPC_BASE 0x0000
25 #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
26 #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
27 #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
28 #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
[all …]
/Linux-v6.1/drivers/video/fbdev/
Dw100fb.h20 #define mmCHIP_ID 0x0000
21 #define mmREVISION_ID 0x0004
22 #define mmWRAP_BUF_A 0x0008
23 #define mmWRAP_BUF_B 0x000C
24 #define mmWRAP_TOP_DIR 0x0010
25 #define mmWRAP_START_DIR 0x0014
26 #define mmCIF_CNTL 0x0018
27 #define mmCFGREG_BASE 0x001C
28 #define mmCIF_IO 0x0020
29 #define mmCIF_READ_DBG 0x0024
[all …]
/Linux-v6.1/drivers/edac/
Die31200_edac.c19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/umc/
Dumc_6_7_0_offset.h29 // base address: 0x50f00
30 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
31 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
32 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
33 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
34 …MCA_UMC_UMC0_MCUMC_MISC0T0 0x03c6
35 …e regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 0
36 …MCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca
37 …e regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 0
38 …MCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtl8xxxu/
Drtl8xxxu_regs.h8 /* 0x0000 ~ 0x00FF System Configuration */
9 #define REG_SYS_ISO_CTRL 0x0000
10 #define SYS_ISO_MD2PP BIT(0)
16 #define REG_SYS_FUNC 0x0002
17 #define SYS_FUNC_BBRSTB BIT(0)
34 #define REG_APS_FSMCO 0x0004
46 #define REG_SYS_CLKR 0x0008
47 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
59 #define REG_9346CR 0x000a
63 #define REG_EE_VPD 0x000c
[all …]
/Linux-v6.1/drivers/clk/qcom/
Dgcc-msm8994.c34 .offset = 0,
37 .enable_reg = 0x1480,
38 .enable_mask = BIT(0),
51 .offset = 0,
64 .offset = 0x1dc0,
67 .enable_reg = 0x1480,
81 .offset = 0x1dc0,
95 { P_XO, 0 },
105 { P_XO, 0 },
117 F(50000000, P_GPLL0, 12, 0, 0),
[all …]
Dgcc-msm8974.c36 { P_XO, 0 },
46 { P_XO, 0 },
58 .l_reg = 0x0004,
59 .m_reg = 0x0008,
60 .n_reg = 0x000c,
61 .config_reg = 0x0014,
62 .mode_reg = 0x0000,
63 .status_reg = 0x001c,
74 .enable_reg = 0x1480,
75 .enable_mask = BIT(0),
[all …]

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