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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-pcs-usb-v5.h10 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
Dphy-qcom-qmp-pcs-usb-v4.h10 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
Dphy-qcom-qmp-pcs-v2.h10 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
12 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
13 #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
14 #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
15 #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
16 #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
18 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
19 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
[all …]
Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_PER1 0x01c
12 #define QSERDES_PLL_SSC_PER2 0x020
13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
18 #define QSERDES_PLL_CLK_ENABLE1 0x040
19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt7986-topckgen.c178 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
180 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
182 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
184 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
187 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
189 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
190 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
/Linux-v6.1/drivers/gpu/drm/vc4/
Dvc4_hdmi_regs.h8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
166 VC4_HD_REG(HDMI_M_CTL, 0x000c),
167 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
168 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
169 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
170 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
171 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
172 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
173 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
/Linux-v6.1/arch/arm64/boot/dts/hisilicon/
Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/Linux-v6.1/drivers/video/fbdev/via/
Daccel.h14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
/Linux-v6.1/drivers/media/platform/mediatek/mdp3/
Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
Dmdp_reg_wdma.h10 #define WDMA_EN 0x008
11 #define WDMA_RST 0x00c
12 #define WDMA_CFG 0x014
13 #define WDMA_SRC_SIZE 0x018
14 #define WDMA_CLIP_SIZE 0x01c
15 #define WDMA_CLIP_COORD 0x020
16 #define WDMA_DST_W_IN_BYTE 0x028
17 #define WDMA_ALPHA 0x02c
18 #define WDMA_BUF_CON2 0x03c
19 #define WDMA_DST_UV_PITCH 0x078
[all …]
Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-driver-jz4780-efuse10 0x000 64 bit Random Number
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
13 0x028 3520 bit Reserved
14 0x1E0 8 bit Protect Segment
15 0x1E1 2296 bit HDMI Key
16 0x300 2048 bit Security boot key
/Linux-v6.1/arch/arm/boot/dts/
Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/Linux-v6.1/include/linux/amba/
Dsp810.h18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
/Linux-v6.1/drivers/bus/
Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/Linux-v6.1/sound/soc/meson/
Daiu.h18 PCLK = 0,
63 #define AIU_IEC958_BPF 0x000
64 #define AIU_958_MISC 0x010
65 #define AIU_IEC958_DCU_FF_CTRL 0x01c
66 #define AIU_958_CHSTAT_L0 0x020
67 #define AIU_958_CHSTAT_L1 0x024
68 #define AIU_958_CTRL 0x028
69 #define AIU_I2S_SOURCE_DESC 0x034
70 #define AIU_I2S_DAC_CFG 0x040
71 #define AIU_I2S_SYNC 0x044
[all …]
/Linux-v6.1/drivers/staging/media/rkvdec/
Drkvdec-regs.h7 #define RKVDEC_REG_INTERRUPT 0x004
8 #define RKVDEC_INTERRUPT_DEC_E BIT(0)
32 #define RKVDEC_REG_SYSCTRL 0x008
33 #define RKVDEC_IN_ENDIAN BIT(0)
44 #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
45 #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
55 #define RKVDEC_REG_PICPAR 0x00C
56 #define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
58 #define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
59 #define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
[all …]
/Linux-v6.1/arch/m68k/ifpsp060/
Disp.doc112 bra _060ISP_TOP+128+0
116 point is located 0 bytes from the top of the "Entry-point" section.)
123 0x000: _060_real_chk
124 0x004: _060_real_divbyzero
125 0x008: _060_real_trace
126 0x00c: _060_real_access
127 0x010: _060_isp_done
129 0x014: _060_real_cas
130 0x018: _060_real_cas2
131 0x01c: _060_real_lock_page
[all …]
/Linux-v6.1/drivers/media/cec/platform/tegra/
Dtegra_cec.h18 #define TEGRA_CEC_SW_CONTROL 0x000
19 #define TEGRA_CEC_HW_CONTROL 0x004
20 #define TEGRA_CEC_INPUT_FILTER 0x008
21 #define TEGRA_CEC_TX_REGISTER 0x010
22 #define TEGRA_CEC_RX_REGISTER 0x014
23 #define TEGRA_CEC_RX_TIMING_0 0x018
24 #define TEGRA_CEC_RX_TIMING_1 0x01c
25 #define TEGRA_CEC_RX_TIMING_2 0x020
26 #define TEGRA_CEC_TX_TIMING_0 0x024
27 #define TEGRA_CEC_TX_TIMING_1 0x028
[all …]
/Linux-v6.1/drivers/hwtracing/coresight/
Dcoresight-catu.h14 #define CATU_CONTROL 0x000
15 #define CATU_MODE 0x004
16 #define CATU_AXICTRL 0x008
17 #define CATU_IRQEN 0x00c
18 #define CATU_SLADDRLO 0x020
19 #define CATU_SLADDRHI 0x024
20 #define CATU_INADDRLO 0x028
21 #define CATU_INADDRHI 0x02c
22 #define CATU_STATUS 0x100
23 #define CATU_DEVARCH 0xfbc
[all …]

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