Lines Matching +full:0 +full:x028
18 #define TEGRA_CEC_SW_CONTROL 0x000
19 #define TEGRA_CEC_HW_CONTROL 0x004
20 #define TEGRA_CEC_INPUT_FILTER 0x008
21 #define TEGRA_CEC_TX_REGISTER 0x010
22 #define TEGRA_CEC_RX_REGISTER 0x014
23 #define TEGRA_CEC_RX_TIMING_0 0x018
24 #define TEGRA_CEC_RX_TIMING_1 0x01c
25 #define TEGRA_CEC_RX_TIMING_2 0x020
26 #define TEGRA_CEC_TX_TIMING_0 0x024
27 #define TEGRA_CEC_TX_TIMING_1 0x028
28 #define TEGRA_CEC_TX_TIMING_2 0x02c
29 #define TEGRA_CEC_INT_STAT 0x030
30 #define TEGRA_CEC_INT_MASK 0x034
31 #define TEGRA_CEC_HW_DEBUG_RX 0x038
32 #define TEGRA_CEC_HW_DEBUG_TX 0x03c
34 #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7fff
44 #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT 0
46 #define TEGRA_CEC_TX_REG_DATA_SHIFT 0
52 #define TEGRA_CEC_RX_REGISTER_SHIFT 0
56 #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT 0
61 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT 0
66 #define TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT 0
68 #define TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT 0
73 #define TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT 0
78 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT 0
82 #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY BIT(0)
96 #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY BIT(0)
110 #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT 0