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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,qmp-ufs-phy.yaml68 "^phy@[0-9a-f]+$":
77 const: 0
168 "^phy@[0-9a-f]+$":
186 "^phy@[0-9a-f]+$":
204 "^phy@[0-9a-f]+$":
218 reg = <0x01d87000 0xe10>;
221 ranges = <0x0 0x01d87000 0x1000>;
226 resets = <&ufs_mem_hc 0>;
233 reg = <0x400 0x108>,
234 <0x600 0x1e0>,
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsm6350.dtsi25 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
63 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
175 #size-cells = <0>;
177 CPU0: cpu@0 {
180 reg = <0x0 0x0>;
186 qcom,freq-domain = <&cpufreq_hw 0>;
201 reg = <0x0 0x100>;
207 qcom,freq-domain = <&cpufreq_hw 0>;
219 reg = <0x0 0x200>;
225 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi30 #clock-cells = <0>;
38 #clock-cells = <0>;
41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
44 #clock-cells = <0>;
50 #clock-cells = <0>;
53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
56 #clock-cells = <0>;
62 #size-cells = <0>;
64 CPU0: cpu@0 {
67 reg = <0x0 0x0>;
[all …]
Dsm8450.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x100>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
73 reg = <0x0 0x100>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
95 reg = <0x0 0x200>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi75 reg = <0 0x80000000 0 0>;
84 reg = <0 0x85700000 0 0x600000>;
89 reg = <0 0x85e00000 0 0x100000>;
94 reg = <0 0x85fc0000 0 0x20000>;
100 reg = <0x0 0x85fe0000 0 0x20000>;
106 reg = <0x0 0x86000000 0 0x200000>;
112 reg = <0 0x86200000 0 0x2d00000>;
118 reg = <0 0x88f00000 0 0x200000>;
126 reg = <0 0x8ab00000 0 0x1400000>;
131 reg = <0 0x8bf00000 0 0x500000>;
[all …]
Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
123 reg = <0x0 0x100>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
144 reg = <0x0 0x200>;
151 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]