Lines Matching +full:0 +full:x01d87000
25 #clock-cells = <0>;
30 #clock-cells = <0>;
175 #size-cells = <0>;
177 CPU0: cpu@0 {
180 reg = <0x0 0x0>;
186 qcom,freq-domain = <&cpufreq_hw 0>;
201 reg = <0x0 0x100>;
207 qcom,freq-domain = <&cpufreq_hw 0>;
219 reg = <0x0 0x200>;
225 qcom,freq-domain = <&cpufreq_hw 0>;
237 reg = <0x0 0x300>;
243 qcom,freq-domain = <&cpufreq_hw 0>;
255 reg = <0x0 0x400>;
273 reg = <0x0 0x500>;
291 reg = <0x0 0x600>;
309 reg = <0x0 0x700>;
363 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
366 arm,psci-suspend-param = <0x40000004>;
373 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
376 arm,psci-suspend-param = <0x40000004>;
385 CLUSTER_SLEEP_0: cluster-sleep-0 {
388 arm,psci-suspend-param = <0x4100c344>;
477 reg = <0x0 0x80000000 0x0 0x0>;
490 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
502 #power-domain-cells = <0>;
508 #power-domain-cells = <0>;
514 #power-domain-cells = <0>;
520 #power-domain-cells = <0>;
526 #power-domain-cells = <0>;
532 #power-domain-cells = <0>;
538 #power-domain-cells = <0>;
563 reg = <0 0x80000000 0 0x860000>;
569 reg = <0 0x80860000 0 0x20000>;
574 reg = <0 0x80880000 0 0x80000>;
580 reg = <0 0x80900000 0 0x200000>;
586 reg = <0 0x80b00000 0 0x100000>;
591 reg = <0 0x83b00000 0 0x1700000>;
596 reg = <0 0x85b00000 0 0xc00000>;
601 reg = <0 0x86c00000 0 0x2000000>;
606 reg = <0 0x8a100000 0 0x1e00000>;
611 reg = <0 0x8c600000 0 0x1e00000>;
616 reg = <0 0xaeb00000 0 0x16600000>;
630 qcom,local-pid = <0>;
654 qcom,local-pid = <0>;
678 qcom,local-pid = <0>;
693 soc: soc@0 {
697 ranges = <0 0 0 0 0x10 0>;
698 dma-ranges = <0 0 0 0 0x10 0>;
702 reg = <0x0 0x00100000 0x0 0x1f0000>;
708 <0>,
709 <0>,
710 <0>,
711 <0>,
712 <0>,
713 <0>,
715 <0>,
716 <0>,
717 <0>,
718 <0>,
719 <0>,
720 <0>,
721 <0>,
723 <0>,
724 <0>,
725 <0>,
726 <0>,
727 <0>,
728 <0>,
729 <0>,
730 <0>,
731 <0>,
732 <0>,
733 <0>,
734 <0>,
735 <0>,
736 <0>,
737 <0>,
738 <0>;
744 reg = <0 0x00408000 0 0x1000>;
753 reg = <0 0x008c0000 0 0x2000>;
757 iommus = <&apps_smmu 0xa3 0>;
767 reg = <0 0x00884000 0 0x4000>;
773 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
774 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
781 reg = <0 0x00894000 0 0x4000>;
786 #size-cells = <0>;
788 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
790 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
798 reg = <0 0x009c0000 0 0x6000>;
802 iommus = <&apps_smmu 0x563 0>;
812 reg = <0 0x00990000 0 0x4000>;
817 #size-cells = <0>;
819 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
821 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
829 reg = <0 0x00ac0000 0 0x6000>;
833 iommus = <&apps_smmu 0x83 0>;
845 reg = <0 0x01d84000 0 0x3000>;
857 iommus = <&apps_smmu 0xe0 0x0>;
876 <0 0>,
877 <0 0>,
879 <0 0>,
880 <0 0>,
881 <0 0>,
882 <0 0>;
888 reg = <0 0x01d87000 0 0x1c8>;
897 resets = <&ufs_mem_hc 0>;
902 reg = <0 0x01d87400 0 0x108>,
903 <0 0x01d87600 0 0x1e0>,
904 <0 0x01d87c00 0 0x1dc>,
905 <0 0x01d87800 0 0x108>,
906 <0 0x01d87a00 0 0x1e0>;
907 #phy-cells = <0>;
914 reg = <0 0x01da4000 0 0x3000>;
925 iommus = <&apps_smmu 0x4a0 0x0>;
944 <0 0>,
945 <0 0>,
947 <0 0>,
948 <0 0>,
949 <0 0>,
950 <0 0>;
956 reg = <0 0x01da7000 0 0x1c8>;
965 resets = <&ufs_card_hc 0>;
971 reg = <0 0x01da7400 0 0x108>,
972 <0 0x01da7600 0 0x1e0>,
973 <0 0x01da7c00 0 0x1dc>,
974 <0 0x01da7800 0 0x108>,
975 <0 0x01da7a00 0 0x1e0>;
976 #phy-cells = <0>;
982 reg = <0x0 0x01f40000 0x0 0x20000>;
989 reg = <0 0x088e5000 0 0x400>;
994 #phy-cells = <0>;
1002 reg = <0 0x088e7000 0 0x400>;
1007 #phy-cells = <0>;
1015 reg = <0 0x088e8000 0 0x400>;
1020 #phy-cells = <0>;
1028 reg = <0 0x088e9000 0 0x400>;
1033 #phy-cells = <0>;
1041 reg = <0 0x088ea000 0 0x400>;
1046 #phy-cells = <0>;
1053 reg = <0 0x088ef000 0 0x1c8>;
1073 reg = <0 0x088efe00 0 0x160>,
1074 <0 0x088f0000 0 0x1ec>,
1075 <0 0x088ef200 0 0x1f0>;
1076 #phy-cells = <0>;
1077 #clock-cells = <0>;
1086 reg = <0 0x088f1000 0 0x1c8>;
1106 reg = <0 0x088f1e00 0 0x160>,
1107 <0 0x088f2000 0 0x1ec>,
1108 <0 0x088f1200 0 0x1f0>;
1109 #phy-cells = <0>;
1110 #clock-cells = <0>;
1119 reg = <0 0x03000000 0 0x100>;
1122 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1141 qcom,smem-states = <&smp2p_adsp_out 0>;
1160 reg = <0 0x088ec000 0 0x1e4>,
1161 <0 0x088eb000 0 0x40>,
1162 <0 0x088ed000 0 0x1c8>;
1182 reg = <0 0x088eb400 0 0x100>,
1183 <0 0x088eb600 0 0x3ec>,
1184 <0 0x088ec400 0 0x364>,
1185 <0 0x088eba00 0 0x100>,
1186 <0 0x088ebc00 0 0x3ec>,
1187 <0 0x088ec200 0 0x18>;
1188 #phy-cells = <0>;
1189 #clock-cells = <0>;
1199 reg = <0 0x08902000 0 0x400>;
1200 #phy-cells = <0>;
1212 reg = <0 0x08904000 0 0x1e4>,
1213 <0 0x08903000 0 0x40>,
1214 <0 0x08905000 0 0x1c8>;
1234 reg = <0 0x08903400 0 0x100>,
1235 <0 0x08903600 0 0x3ec>,
1236 <0 0x08904400 0 0x364>,
1237 <0 0x08903a00 0 0x100>,
1238 <0 0x08903c00 0 0x3ec>,
1239 <0 0x08904200 0 0x18>;
1240 #phy-cells = <0>;
1241 #clock-cells = <0>;
1250 reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1257 reg = <0 0x0a6f8800 0 0x400>;
1291 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1292 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1301 reg = <0 0x0a600000 0 0xcd00>;
1303 iommus = <&apps_smmu 0x820 0x0>;
1311 reg = <0 0x0a8f8800 0 0x400>;
1345 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1355 reg = <0 0x0a800000 0 0xcd00>;
1357 iommus = <&apps_smmu 0x860 0x0>;
1365 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1366 qcom,pdc-ranges = <0 480 40>,
1430 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1431 <0 0x0c222000 0 0x8>; /* SROT */
1441 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1442 <0 0x0c223000 0 0x8>; /* SROT */
1452 reg = <0 0x0c300000 0 0x400>;
1456 #clock-cells = <0>;
1461 reg = <0 0x0c440000 0 0x1100>,
1462 <0 0x0c600000 0 0x2000000>,
1463 <0 0x0e600000 0 0x100000>,
1464 <0 0x0e700000 0 0xa0000>,
1465 <0 0x0c40a000 0 0x26000>;
1469 qcom,ee = <0>;
1470 qcom,channel = <0>;
1479 reg = <0 0x0f100000 0 0x300000>;
1485 gpio-ranges = <&tlmm 0 0 230>;
1490 reg = <0 0x15000000 0 0x100000>;
1629 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1630 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1633 redistributor-stride = <0 0x20000>;
1641 reg = <0 0x17a40000 0 0x20000>;
1649 reg = <0 0x17c10000 0 0x1000>;
1651 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1656 reg = <0x0 0x17c20000 0x0 0x1000>;
1659 ranges = <0x0 0x0 0x0 0x20000000>;
1662 frame-number = <0>;
1665 reg = <0x17c21000 0x1000>,
1666 <0x17c22000 0x1000>;
1672 reg = <0x17c23000 0x1000>;
1679 reg = <0x17c25000 0x1000>;
1686 reg = <0x17c26000 0x1000>;
1693 reg = <0x17c29000 0x1000>;
1700 reg = <0x17c2b000 0x1000>;
1707 reg = <0x17c2d000 0x1000>;
1714 reg = <0x0 0x18200000 0x0 0x10000>,
1715 <0x0 0x18210000 0x0 0x10000>,
1716 <0x0 0x18220000 0x0 0x10000>;
1717 reg-names = "drv-0", "drv-1", "drv-2";
1721 qcom,tcs-offset = <0xd00>;
1791 reg = <0 0x18591000 0 0x1000>,
1792 <0 0x18592000 0 0x1000>;
1803 reg = <0 0x1b300000 0 0x100>;
1806 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
1821 qcom,smem-states = <&smp2p_nsp0_out 0>;
1824 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
1843 #size-cells = <0>;
1848 iommus = <&apps_smmu 0x3181 0x0420>;
1854 iommus = <&apps_smmu 0x3182 0x0420>;
1860 iommus = <&apps_smmu 0x3183 0x0420>;
1866 iommus = <&apps_smmu 0x3184 0x0420>;
1872 iommus = <&apps_smmu 0x3185 0x0420>;
1878 iommus = <&apps_smmu 0x3186 0x0420>;
1884 iommus = <&apps_smmu 0x3187 0x0420>;
1890 iommus = <&apps_smmu 0x3188 0x0420>;
1896 iommus = <&apps_smmu 0x318b 0x0420>;
1902 iommus = <&apps_smmu 0x318b 0x0420>;
1908 iommus = <&apps_smmu 0x318c 0x0420>;
1914 iommus = <&apps_smmu 0x318d 0x0420>;
1920 iommus = <&apps_smmu 0x318e 0x0420>;
1926 iommus = <&apps_smmu 0x318f 0x0420>;
1934 reg = <0 0x21300000 0 0x100>;
1937 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
1952 qcom,smem-states = <&smp2p_nsp1_out 0>;
1955 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;