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/Linux-v5.15/arch/arm/mach-s3c/
Dvr1000.h14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/interconnect/
Dqcom,sdm660.yaml124 reg = <0x01008000 0x78000>;
133 reg = <0x01500000 0x10000>;
142 reg = <0x01626000 0x7090>;
151 reg = <0x01704000 0xc100>;
171 reg = <0x01745000 0xa010>;
181 reg = <0x17900000 0xe000>;
/Linux-v5.15/arch/mips/include/asm/sn/sn0/
Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/Linux-v5.15/arch/arm/net/
Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/Linux-v5.15/drivers/staging/media/tegra-vde/
Dvde.c31 #define ICMDQUE_WR 0x00
32 #define CMDQUE_CONTROL 0x08
33 #define INTR_STATUS 0x18
34 #define BSE_INT_ENB 0x40
35 #define BSE_CONFIG 0x44
83 return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp, in tegra_vde_wait_mbe()
84 (tmp >= 0x10), 1, 100); in tegra_vde_wait_mbe()
91 u32 frame_idx_enb_mask = 0; in tegra_vde_setup_mbe_frame_idx()
97 tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
98 tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
[all …]
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsm8350.dtsi28 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x200>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm630.dtsi27 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
47 reg = <0x0 0x100>;
66 reg = <0x0 0x101>;
81 reg = <0x0 0x102>;
96 reg = <0x0 0x103>;
108 CPU4: cpu@0 {
111 reg = <0x0 0x0>;
130 reg = <0x0 0x1>;
[all …]
Dsc7280.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
53 reg = <0x0 0x80800000 0x0 0x60000>;
58 reg = <0x0 0x80860000 0x0 0x20000>;
64 reg = <0x0 0x80900000 0x0 0x200000>;
70 reg = <0x0 0x80b00000 0x0 0x100000>;
74 reg = <0 0x8b700000 0 0x10000>;
81 #size-cells = <0>;
83 CPU0: cpu@0 {
86 reg = <0x0 0x0>;
[all …]
Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
74 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0x0 0x200>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi62 #clock-cells = <0>;
68 #clock-cells = <0>;
78 reg = <0x0 0x80000000 0x0 0x600000>;
83 reg = <0x0 0x80600000 0x0 0x200000>;
88 reg = <0x0 0x80800000 0x0 0x20000>;
93 reg = <0x0 0x80820000 0x0 0x20000>;
99 reg = <0x0 0x808ff000 0x0 0x1000>;
104 reg = <0x0 0x80900000 0x0 0x200000>;
109 reg = <0x0 0x80b00000 0x0 0x3900000>;
114 reg = <0 0x8b700000 0 0x10000>;
[all …]
Dsm8250.dtsi78 #clock-cells = <0>;
86 #clock-cells = <0>;
92 #size-cells = <0>;
94 CPU0: cpu@0 {
97 reg = <0x0 0x0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
116 reg = <0x0 0x100>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
132 reg = <0x0 0x200>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]