| /Linux-v6.6/sound/drivers/ |
| D | serial-u16550.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Added support for the Midiator MS-124T and for the MS-124W in
17 * More documentation can be found in serial-u16550.txt.
39 #define SNDRV_SERIAL_MS124T 1 /* Midiator MS-124T */
40 #define SNDRV_SERIAL_MS124W_SA 2 /* Midiator MS-124W in S/A mode */
41 #define SNDRV_SERIAL_MS124W_MB 3 /* Midiator MS-124W in M/B mode */
46 "MS-124T",
47 "MS-124W S/A",
48 "MS-124W M/B",
53 #define SNDRV_SERIAL_DROPBUFF 1 /* Non-blocking discard operation */
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| /Linux-v6.6/Documentation/devicetree/bindings/serial/ |
| D | mediatek,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
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| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
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| D | amlogic,meson-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
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| D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
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| D | fsl-imx-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
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| D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - items:
22 - const: samsung,exynosautov9-uart
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| D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
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| D | sprd-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Spreadtrum serial UART
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - items:
19 - enum:
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| D | brcm,bcm7271-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
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| D | ingenic,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs UART controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
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| D | 8250_omap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
13 - $ref: /schemas/serial/serial.yaml#
14 - $ref: /schemas/serial/rs485.yaml#
19 - enum:
20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
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| /Linux-v6.6/drivers/tty/serial/ |
| D | men_z135_uart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
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| D | timbuart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
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| D | arc_uart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
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| /Linux-v6.6/drivers/tty/serial/8250/ |
| D | 8250_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
31 status = p->serial_in(p, UART_LSR); in tegra_uart_handle_break()
35 p->serial_in(p, UART_RX); in tegra_uart_handle_break()
37 if (--tmout == 0) in tegra_uart_handle_break()
46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
53 return -ENOMEM; in tegra_uart_probe()
58 spin_lock_init(&port->lock); in tegra_uart_probe()
60 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | in tegra_uart_probe()
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| D | 8250_core.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
48 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
49 * is unsafe when used on edge-triggered interrupts.
63 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * line has been de-asserted.
117 spin_lock(&i->lock); in serial8250_interrupt()
119 l = i->head; in serial8250_interrupt()
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| D | 8250_lpc18xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for NXP LPC18xx/43xx UART
43 if (rs485->flags & SER_RS485_ENABLED) { in lpc18xx_rs485_config()
47 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpc18xx_rs485_config()
51 if (rs485->delay_rts_after_send) { in lpc18xx_rs485_config()
52 baud_clk = port->uartclk / up->dl_read(up); in lpc18xx_rs485_config()
53 rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send in lpc18xx_rs485_config()
60 rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC) in lpc18xx_rs485_config()
80 offset = offset << p->regshift; in lpc18xx_uart_serial_out()
81 writel(value, p->membase + offset); in lpc18xx_uart_serial_out()
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| D | 8250_ingenic.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
46 return readl(port->membase + (offset << 2)); in early_in()
51 writel(value, port->membase + (offset << 2)); in early_out()
68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail()
96 if (!dev->port.membase) in ingenic_earlycon_setup_tail()
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| D | 8250_pxa.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
37 serial8250_suspend_port(data->line); in serial_pxa_suspend()
46 serial8250_resume_port(data->line); in serial_pxa_resume()
56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
85 clk_prepare_enable(data->clk); in serial_pxa_pm()
87 clk_disable_unprepare(data->clk); in serial_pxa_pm()
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| D | 8250_dfl.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA UART
45 return -EINVAL; in dfh_get_u64_param_val()
52 static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) in dfl_uart_get_params() argument
54 struct device *dev = &dfl_dev->dev; in dfl_uart_get_params()
63 uart->port.uartclk = clk_freq; in dfl_uart_get_params()
71 uart->port.type = PORT_ALTR_16550_F32; in dfl_uart_get_params()
75 uart->port.type = PORT_ALTR_16550_F64; in dfl_uart_get_params()
79 uart->port.type = PORT_ALTR_16550_F128; in dfl_uart_get_params()
83 return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len); in dfl_uart_get_params()
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| /Linux-v6.6/include/uapi/linux/ |
| D | serial_core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
34 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
35 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
36 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
37 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
38 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
39 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
43 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
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| /Linux-v6.6/arch/mips/kernel/ |
| D | cps-vec-ns16550.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
46 * @a0: pointer to NULL-terminated ASCII string
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
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| /Linux-v6.6/arch/arm/include/debug/ |
| D | tegra.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
12 * Portions based on mach-omap2's debug-macro.S
13 * Copyright (C) 1994-1999 Russell King
40 * Must be section-aligned since a section mapping is used early on.
41 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
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| /Linux-v6.6/arch/arm/ |
| D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
107 1 - undefined instruction events
108 2 - system calls
109 4 - invalid data aborts
110 8 - SIGSEGV faults
111 16 - SIGBUS faults
115 bool "Kernel low-level debugging functions (read help!)"
123 UART definition, as specified below. Attempting to boot the kernel
128 prompt "Kernel low-level debugging port"
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