1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6  * Ingenic SoC UART support
46 	return readl(port->membase + (offset << 2));  in early_in()
51 	writel(value, port->membase + (offset << 2));  in early_out()
68 	uart_console_write(&early_device->port, s, count,  in ingenic_early_console_write()
82 	prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);  in ingenic_early_console_setup_clock()
86 	dev->port.uartclk = be32_to_cpup(prop);  in ingenic_early_console_setup_clock()
92 	struct uart_port *port = &dev->port;  in ingenic_earlycon_setup_tail()
96 	if (!dev->port.membase)  in ingenic_earlycon_setup_tail()
97 		return -ENODEV;  in ingenic_earlycon_setup_tail()
105 	if (dev->baud)  in ingenic_earlycon_setup_tail()
106 		baud = dev->baud;  in ingenic_earlycon_setup_tail()
107 	divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);  in ingenic_earlycon_setup_tail()
124 	dev->con->write = ingenic_early_console_write;  in ingenic_earlycon_setup_tail()
142 	 * oscillator and some peripherals including UART, which will  in jz4750_early_console_setup()
147 	if (dev->port.uartclk >= 16000000)  in jz4750_early_console_setup()
148 		dev->port.uartclk /= 2;  in jz4750_early_console_setup()
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
177 		/* UART module enable */  in ingenic_uart_serial_out()
194 		ier = p->serial_in(p, UART_IER);  in ingenic_uart_serial_out()
206 	writeb(value, p->membase + (offset << p->regshift));  in ingenic_uart_serial_out()
213 	value = readb(p->membase + (offset << p->regshift));  in ingenic_uart_serial_in()
215 	/* Hide non-16550 compliant bits from higher levels */  in ingenic_uart_serial_in()
233 	struct uart_8250_port uart = {};  in ingenic_uart_probe()  local
239 	cdata = of_device_get_match_data(&pdev->dev);  in ingenic_uart_probe()
241 		dev_err(&pdev->dev, "Error: No device match found\n");  in ingenic_uart_probe()
242 		return -ENODEV;  in ingenic_uart_probe()
251 		dev_err(&pdev->dev, "no registers defined\n");  in ingenic_uart_probe()
252 		return -EINVAL;  in ingenic_uart_probe()
255 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);  in ingenic_uart_probe()
257 		return -ENOMEM;  in ingenic_uart_probe()
259 	spin_lock_init(&uart.port.lock);  in ingenic_uart_probe()
260 	uart.port.type = PORT_16550A;  in ingenic_uart_probe()
261 	uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;  in ingenic_uart_probe()
262 	uart.port.iotype = UPIO_MEM;  in ingenic_uart_probe()
263 	uart.port.mapbase = regs->start;  in ingenic_uart_probe()
264 	uart.port.regshift = 2;  in ingenic_uart_probe()
265 	uart.port.serial_out = ingenic_uart_serial_out;  in ingenic_uart_probe()
266 	uart.port.serial_in = ingenic_uart_serial_in;  in ingenic_uart_probe()
267 	uart.port.irq = irq;  in ingenic_uart_probe()
268 	uart.port.dev = &pdev->dev;  in ingenic_uart_probe()
269 	uart.port.fifosize = cdata->fifosize;  in ingenic_uart_probe()
270 	uart.tx_loadsz = cdata->tx_loadsz;  in ingenic_uart_probe()
271 	uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;  in ingenic_uart_probe()
274 	line = of_alias_get_id(pdev->dev.of_node, "serial");  in ingenic_uart_probe()
276 		uart.port.line = line;  in ingenic_uart_probe()
278 	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,  in ingenic_uart_probe()
280 	if (!uart.port.membase)  in ingenic_uart_probe()
281 		return -ENOMEM;  in ingenic_uart_probe()
283 	data->clk_module = devm_clk_get(&pdev->dev, "module");  in ingenic_uart_probe()
284 	if (IS_ERR(data->clk_module))  in ingenic_uart_probe()
285 		return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),  in ingenic_uart_probe()
288 	data->clk_baud = devm_clk_get(&pdev->dev, "baud");  in ingenic_uart_probe()
289 	if (IS_ERR(data->clk_baud))  in ingenic_uart_probe()
290 		return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),  in ingenic_uart_probe()
293 	err = clk_prepare_enable(data->clk_module);  in ingenic_uart_probe()
295 		dev_err(&pdev->dev, "could not enable module clock: %d\n", err);  in ingenic_uart_probe()
299 	err = clk_prepare_enable(data->clk_baud);  in ingenic_uart_probe()
301 		dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);  in ingenic_uart_probe()
304 	uart.port.uartclk = clk_get_rate(data->clk_baud);  in ingenic_uart_probe()
306 	data->line = serial8250_register_8250_port(&uart);  in ingenic_uart_probe()
307 	if (data->line < 0) {  in ingenic_uart_probe()
308 		err = data->line;  in ingenic_uart_probe()
316 	clk_disable_unprepare(data->clk_baud);  in ingenic_uart_probe()
318 	clk_disable_unprepare(data->clk_module);  in ingenic_uart_probe()
327 	serial8250_unregister_port(data->line);  in ingenic_uart_remove()
328 	clk_disable_unprepare(data->clk_module);  in ingenic_uart_remove()
329 	clk_disable_unprepare(data->clk_baud);  in ingenic_uart_remove()
354 	{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
355 	{ .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config },
356 	{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
357 	{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
358 	{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
359 	{ .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
360 	{ .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
367 		.name		= "ingenic-uart",
378 MODULE_DESCRIPTION("Ingenic SoC UART driver");