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/Linux-v5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
/Linux-v5.10/drivers/misc/
Dsram.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Generic on-chip SRAM allocation driver
19 #include <soc/at91/atmel-secumod.h>
21 #include "sram.h"
33 mutex_lock(&part->lock); in sram_read()
34 memcpy_fromio(buf, part->base + pos, count); in sram_read()
35 mutex_unlock(&part->lock); in sram_read()
48 mutex_lock(&part->lock); in sram_write()
49 memcpy_toio(part->base + pos, buf, count); in sram_write()
50 mutex_unlock(&part->lock); in sram_write()
[all …]
Dsram-exec.c2 * SRAM protect-exec region helper functions
4 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
20 #include <linux/sram.h>
25 #include "sram.h"
30 int sram_check_protect_exec(struct sram_dev *sram, struct sram_reserve *block, in sram_check_protect_exec() argument
33 unsigned long base = (unsigned long)part->base; in sram_check_protect_exec()
34 unsigned long end = base + block->size; in sram_check_protect_exec()
37 dev_err(sram->dev, in sram_check_protect_exec()
38 "SRAM pool marked with 'protect-exec' is not page aligned and will not be created.\n"); in sram_check_protect_exec()
39 return -ENOMEM; in sram_check_protect_exec()
[all …]
/Linux-v5.10/arch/arm/plat-omap/
Dsram.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-omap/sram.c
5 * OMAP SRAM detection and management
10 * Copyright (C) 2009-2012 Texas Instruments
11 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <plat/sram.h>
29 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
37 * Memory allocator for SRAM: calculates the new ceiling address
41 * to an 8-byte boundary.
47 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); in omap_sram_push_address()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dcache_sram.txt1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
6 tree should be done as under:-
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
/Linux-v5.10/arch/arm/boot/dts/
Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
[all …]
Dlpc4357.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
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/Linux-v5.10/arch/arm/mach-davinci/
Dsram.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * mach/sram.h - DaVinci simple SRAM allocator
10 /* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14 * SRAM allocations return a CPU virtual address, or NULL on error.
15 * If a DMA address is requested and the SRAM supports DMA, its
18 * Errors include SRAM memory not being available, and requesting
19 * DMA mapped SRAM on systems which don't allow that.
/Linux-v5.10/drivers/mtd/devices/
Dms02-nv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for
16 * 0x000000 - 0x3fffff SRAM
17 * 0x400000 - 0x7fffff CSR
19 * Within the SRAM area the following ranges are forced by the system
22 * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot
23 * 0x000400 - ENDofRAM storage area, available to operating systems
28 * ID value is found, the firmware considers the SRAM clean, i.e.
31 * for the start address of the user-available is 0x001000 which is
36 * operating system, a magic ID to distinguish a MS02-NV board from
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/Linux-v5.10/Documentation/devicetree/bindings/crypto/
Dmv_cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 - reg: base physical address of the engine and length of memory mapped
9 region. Can also contain an entry for the SRAM attached to the CESA,
10 but this representation is deprecated and marvell,crypto-srams should
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
13 is deprecated and marvell,crypto-srams should be used instead
14 - interrupts: interrupt number
[all …]
Dmarvell-cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 "marvell,armada-370-crypto"
9 "marvell,armada-xp-crypto"
10 "marvell,armada-375-crypto"
11 "marvell,armada-38x-crypto"
12 - reg: base physical address of the engine and length of memory mapped
13 region. Can also contain an entry for the SRAM attached to the CESA,
[all …]
/Linux-v5.10/arch/powerpc/platforms/52xx/
Dmpc52xx_pm.c1 // SPDX-License-Identifier: GPL-2.0
10 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
22 static void __iomem *sram; variable
42 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
44 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
46 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
48 tmp = in_be16(&gpiow->wkup_itype); in mpc52xx_set_wakeup_gpio()
51 out_be16(&gpiow->wkup_itype, tmp); in mpc52xx_set_wakeup_gpio()
53 out_8(&gpiow->wkup_maste, 1); in mpc52xx_set_wakeup_gpio()
62 { .compatible = "fsl,mpc5200-immr", }, in mpc52xx_pm_prepare()
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/Linux-v5.10/drivers/net/wireless/ath/ath9k/
Dar9003_aic.c18 #include "hw-ops.h"
42 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; in ar9003_hw_is_aic_enabled()
46 * HW code and the driver-layer support ready. in ar9003_hw_is_aic_enabled()
50 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_AIC) in ar9003_hw_is_aic_enabled()
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
74 i = -1; in ar9003_aic_find_valid()
84 int16_t i = -1; in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
94 i--; in ar9003_aic_find_index()
100 i = -1; in ar9003_aic_find_index()
[all …]
/Linux-v5.10/arch/arm/mach-omap1/
Dsram-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP SRAM detection and management
21 #include "sram.h"
27 * The amount of SRAM depends on the core type.
28 * Note that we cannot try to test for SRAM here because writes
29 * to secure SRAM will hang the system. Also the SRAM is not
46 pr_err("Could not detect SRAM size\n"); in omap_detect_and_map_sram()
/Linux-v5.10/arch/arm/mach-omap2/
Dsram.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * OMAP SRAM detection and management
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
28 #include "sram.h"
47 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
55 * SRAM varies. The default accessible size for all device types is 2k. A GP
64 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
65 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ in is_sram_locked()
66 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ in is_sram_locked()
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/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
/Linux-v5.10/drivers/memory/
Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/Linux-v5.10/drivers/crypto/ccree/
Dcc_sram_mgr.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
13 #define NULL_SRAM_ADDR ((u32)-1)
16 * cc_sram_mgr_init() - Initializes SRAM pool.
17 * The first X bytes of SRAM are reserved for ROM usage, hence, pool
28 * cc_sram_alloc() - Allocate buffer from SRAM pool.
34 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
39 * cc_set_sram_desc() - Create const descriptors sequence to
40 * set values in given array into SRAM.
44 * @dst: The target SRAM buffer to set into
Dcc_sram_mgr.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
8 * cc_sram_mgr_init() - Initializes SRAM pool.
9 * The pool starts right at the beginning of SRAM.
22 if (drvdata->hw_rev < CC_HW_REV_712) { in cc_sram_mgr_init()
26 dev_err(dev, "Invalid SRAM offset 0x%x\n", start); in cc_sram_mgr_init()
27 return -EINVAL; in cc_sram_mgr_init()
31 drvdata->sram_free_offset = start; in cc_sram_mgr_init()
36 * cc_sram_alloc() - Allocate buffer from SRAM pool.
42 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
[all …]
/Linux-v5.10/drivers/fsi/
Dfsi-master-ast-cf.c1 // SPDX-License-Identifier: GPL-2.0+
4 * A FSI master controller, using a simple GPIO bit-banging interface
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
82 /* Amount of SRAM required */
111 void __iomem *sram; member
132 msg->msg <<= bits; in msg_push_bits()
133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()
134 msg->bits += bits; in msg_push_bits()
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/Linux-v5.10/drivers/media/pci/cx25821/
Dcx25821-sram.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
17 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */
26 /* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */
27 /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
29 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
36 /* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */
37 /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
39 /* Receive SRAM */
167 /* Free Receive SRAM 144 Bytes */
[all …]
/Linux-v5.10/drivers/media/common/b2c2/
Dflexcop-sram.c1 // SPDX-License-Identifier: GPL-2.0
4 * flexcop-sram.c - functions for controlling the SRAM
17 switch (fc->rev) { in flexcop_sram_init()
26 return -EINVAL; in flexcop_sram_init()
35 v = fc->read_ibi_reg(fc, sram_dest_reg_714); in flexcop_sram_set_dest()
37 if (fc->rev != FLEXCOP_III && target == FC_SRAM_DEST_TARGET_FC3_CA) { in flexcop_sram_set_dest()
38 err("SRAM destination target to available on FlexCopII(b)\n"); in flexcop_sram_set_dest()
39 return -EINVAL; in flexcop_sram_set_dest()
41 deb_sram("sram dest: %x target: %x\n", dest, target); in flexcop_sram_set_dest()
52 fc->write_ibi_reg(fc,sram_dest_reg_714,v); in flexcop_sram_set_dest()
[all …]
/Linux-v5.10/drivers/soc/sunxi/
Dsunxi_sram.c2 * Allwinner SoCs SRAM Controller Driver
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
91 .compatible = "allwinner,sun4i-a10-sram-c1",
95 .compatible = "allwinner,sun4i-a10-sram-d",
99 .compatible = "allwinner,sun50i-a64-sram-c",
119 seq_puts(s, "Allwinner sunXi SRAM\n"); in sunxi_sram_show()
120 seq_puts(s, "--------------------\n\n"); in sunxi_sram_show()
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/Linux-v5.10/Documentation/devicetree/bindings/arm/omap/
Dmpu.txt1 * TI - MPU (Main Processor Unit) subsystem
8 - compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
11 - ti,hwmods: "mpu"
14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
18 First should be type 'protect-exec' for the driver to use to copy
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
25 - For an OMAP5 SMP system:
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