| /Linux-v6.1/arch/arm/boot/dts/ |
| D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
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| D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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| D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
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| D | s3c2416-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include "s3c2410-pinctrl.h"
15 gpa: gpa-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
20 gpb: gpb-gpio-bank {
21 gpio-controller;
22 #gpio-cells = <2>;
25 gpc: gpc-gpio-bank {
26 gpio-controller;
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| D | exynos5260-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
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| D | exynos4412-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
12 #include "exynos-pinctrl.h"
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
26 interrupt-controller;
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| D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
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| /Linux-v6.1/drivers/gpio/ |
| D | gpio-omap.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 #include <linux/gpio/driver.h>
27 #include <linux/platform_data/gpio-omap.h>
77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
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| D | gpio-aspeed-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/driver.h>
48 * Note: The "value" register returns the input value when the GPIO is
51 * The "rdata" register returns the output value when the GPIO is
103 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() argument
104 const struct aspeed_sgpio_bank *bank, in bank_reg() argument
109 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
111 return gpio->base + bank->rdata_reg; in bank_reg()
113 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
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| D | gpio-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/aspeed.h>
23 * These two headers aren't meant to be used by GPIO drivers. We need
28 #include <linux/gpio/consumer.h>
32 unsigned int bank; member
48 * represents disabled debouncing for the GPIO. Any other value for an element
83 * line even when the GPIO is configured as an output. Since
208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() argument
209 const struct aspeed_gpio_bank *bank, in bank_reg() argument
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| D | gpio-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
[all …]
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| D | gpio-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-tegra/gpio.c
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
17 #include <linux/gpio/driver.h>
31 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
45 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
46 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
47 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
48 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
49 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
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| D | gpio-bcm-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Kona GPIO Driver
5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6 * Copyright (C) 2012-2014 Broadcom Corporation
12 #include <linux/gpio/driver.h>
22 #define GPIO_BANK(gpio) ((gpio) >> 5) argument
23 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) argument
25 /* There is a GPIO control register for each GPIO */
26 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) argument
28 /* The remaining registers are per GPIO bank */
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| D | gpio-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/gpio/driver.h>
23 #include <linux/pinctrl/pinconf-generic.h>
27 #include "../pinctrl/pinctrl-rockchip.h"
29 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
30 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
31 #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
[all …]
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| D | gpio-davinci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DaVinci GPIO Support
5 * Copyright (c) 2006-2007 David Brownell
9 #include <linux/gpio/driver.h>
22 #include <linux/platform_data/gpio-davinci.h>
27 #include <asm-generic/gpio.h>
47 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
61 /* Serialize access to GPIO registers */
70 static inline u32 __gpio_mask(unsigned gpio) in __gpio_mask() argument
72 return 1 << (gpio % 32); in __gpio_mask()
[all …]
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| D | gpio-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2015-2017 Broadcom
5 #include <linux/gpio/driver.h>
26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
[all …]
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| /Linux-v6.1/tools/testing/selftests/gpio/ |
| D | gpio-sim.sh | 2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
11 echo "GPIO $MODULE test FAIL"
17 echo "GPIO $MODULE test SKIP"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | egrep ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/tesla/ |
| D | fsd-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
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| D | samsung,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
[all …]
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| /Linux-v6.1/drivers/pinctrl/ |
| D | pinctrl-oxnas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Based on pinctrl-pic32.c
11 #include <linux/gpio/driver.h>
18 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
30 #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) argument
51 /* GPIO Registers */
71 unsigned int bank; member
260 FUNCTION(gpio, ox810se_fct0),
265 FUNCTION(gpio, ox820_fct0),
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/exynos/ |
| D | exynos7-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
[all …]
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| D | exynos5433-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
[all …]
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| D | exynos850-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
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