Lines Matching +full:- +full:gpio +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/driver.h>
48 * Note: The "value" register returns the input value when the GPIO is
51 * The "rdata" register returns the output value when the GPIO is
103 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() argument
104 const struct aspeed_sgpio_bank *bank, in bank_reg() argument
109 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
111 return gpio->base + bank->rdata_reg; in bank_reg()
113 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
121 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
123 return gpio->base + bank->tolerance_regs; in bank_reg()
136 unsigned int bank; in to_bank() local
138 bank = GPIO_BANK(offset); in to_bank()
140 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); in to_bank()
141 return &aspeed_sgpio_banks[bank]; in to_bank()
170 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); in aspeed_sgpio_get() local
171 const struct aspeed_sgpio_bank *bank = to_bank(offset); in aspeed_sgpio_get() local
176 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_get()
179 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
181 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_get()
188 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); in sgpio_set_value() local
189 const struct aspeed_sgpio_bank *bank = to_bank(offset); in sgpio_set_value() local
194 return -EINVAL; in sgpio_set_value()
198 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
199 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
215 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); in aspeed_sgpio_set() local
218 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_set()
222 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_set()
227 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; in aspeed_sgpio_dir_in()
232 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); in aspeed_sgpio_dir_out() local
237 * error-out in sgpio_set_value if this isn't an output GPIO */ in aspeed_sgpio_dir_out()
239 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_dir_out()
241 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_dir_out()
252 struct aspeed_sgpio **gpio, in irqd_to_aspeed_sgpio_data() argument
253 const struct aspeed_sgpio_bank **bank, in irqd_to_aspeed_sgpio_data() argument
262 *gpio = internal; in irqd_to_aspeed_sgpio_data()
263 *bank = to_bank(*offset); in irqd_to_aspeed_sgpio_data()
269 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_irq_ack() local
270 struct aspeed_sgpio *gpio; in aspeed_sgpio_irq_ack() local
276 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_ack()
278 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
280 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_irq_ack()
284 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_irq_ack()
289 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_irq_set_mask() local
290 struct aspeed_sgpio *gpio; in aspeed_sgpio_irq_set_mask() local
296 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_set_mask()
297 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
299 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_irq_set_mask()
309 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_irq_set_mask()
328 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_set_type() local
330 struct aspeed_sgpio *gpio; in aspeed_sgpio_set_type() local
335 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_set_type()
355 return -EINVAL; in aspeed_sgpio_set_type()
358 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_set_type()
360 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
365 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
370 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
375 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_set_type()
393 const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i]; in aspeed_sgpio_irq_handler() local
395 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
398 generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); in aspeed_sgpio_irq_handler()
404 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio, in aspeed_sgpio_setup_irqs() argument
408 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_setup_irqs() local
415 gpio->irq = rc; in aspeed_sgpio_setup_irqs()
419 bank = &aspeed_sgpio_banks[i]; in aspeed_sgpio_setup_irqs()
421 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); in aspeed_sgpio_setup_irqs()
423 iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); in aspeed_sgpio_setup_irqs()
426 gpio->intc.name = dev_name(&pdev->dev); in aspeed_sgpio_setup_irqs()
427 gpio->intc.irq_ack = aspeed_sgpio_irq_ack; in aspeed_sgpio_setup_irqs()
428 gpio->intc.irq_mask = aspeed_sgpio_irq_mask; in aspeed_sgpio_setup_irqs()
429 gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask; in aspeed_sgpio_setup_irqs()
430 gpio->intc.irq_set_type = aspeed_sgpio_set_type; in aspeed_sgpio_setup_irqs()
432 irq = &gpio->chip.irq; in aspeed_sgpio_setup_irqs()
433 irq->chip = &gpio->intc; in aspeed_sgpio_setup_irqs()
434 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask; in aspeed_sgpio_setup_irqs()
435 irq->handler = handle_bad_irq; in aspeed_sgpio_setup_irqs()
436 irq->default_type = IRQ_TYPE_NONE; in aspeed_sgpio_setup_irqs()
437 irq->parent_handler = aspeed_sgpio_irq_handler; in aspeed_sgpio_setup_irqs()
438 irq->parent_handler_data = gpio; in aspeed_sgpio_setup_irqs()
439 irq->parents = &gpio->irq; in aspeed_sgpio_setup_irqs()
440 irq->num_parents = 1; in aspeed_sgpio_setup_irqs()
444 bank = &aspeed_sgpio_banks[i]; in aspeed_sgpio_setup_irqs()
445 /* set falling or level-low irq */ in aspeed_sgpio_setup_irqs()
446 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); in aspeed_sgpio_setup_irqs()
448 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); in aspeed_sgpio_setup_irqs()
450 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); in aspeed_sgpio_setup_irqs()
463 struct aspeed_sgpio *gpio = gpiochip_get_data(chip); in aspeed_sgpio_reset_tolerance() local
468 reg = bank_reg(gpio, to_bank(offset), reg_tolerance); in aspeed_sgpio_reset_tolerance()
470 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_reset_tolerance()
481 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_reset_tolerance()
495 return -ENOTSUPP; in aspeed_sgpio_set_config()
503 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
504 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
505 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
515 struct aspeed_sgpio *gpio; in aspeed_sgpio_probe() local
519 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_sgpio_probe()
520 if (!gpio) in aspeed_sgpio_probe()
521 return -ENOMEM; in aspeed_sgpio_probe()
523 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_sgpio_probe()
524 if (IS_ERR(gpio->base)) in aspeed_sgpio_probe()
525 return PTR_ERR(gpio->base); in aspeed_sgpio_probe()
527 pdata = device_get_match_data(&pdev->dev); in aspeed_sgpio_probe()
529 return -EINVAL; in aspeed_sgpio_probe()
531 pin_mask = pdata->pin_mask; in aspeed_sgpio_probe()
533 rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios); in aspeed_sgpio_probe()
535 dev_err(&pdev->dev, "Could not read ngpios property\n"); in aspeed_sgpio_probe()
536 return -EINVAL; in aspeed_sgpio_probe()
538 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n", in aspeed_sgpio_probe()
540 return -EINVAL; in aspeed_sgpio_probe()
543 rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq); in aspeed_sgpio_probe()
545 dev_err(&pdev->dev, "Could not read bus-frequency property\n"); in aspeed_sgpio_probe()
546 return -EINVAL; in aspeed_sgpio_probe()
549 gpio->pclk = devm_clk_get(&pdev->dev, NULL); in aspeed_sgpio_probe()
550 if (IS_ERR(gpio->pclk)) { in aspeed_sgpio_probe()
551 dev_err(&pdev->dev, "devm_clk_get failed\n"); in aspeed_sgpio_probe()
552 return PTR_ERR(gpio->pclk); in aspeed_sgpio_probe()
555 apb_freq = clk_get_rate(gpio->pclk); in aspeed_sgpio_probe()
564 * GPIO254[31:16] = PCLK / (frequency * 2) - 1 in aspeed_sgpio_probe()
567 return -EINVAL; in aspeed_sgpio_probe()
569 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; in aspeed_sgpio_probe()
571 if (sgpio_clk_div > (1 << 16) - 1) in aspeed_sgpio_probe()
572 return -EINVAL; in aspeed_sgpio_probe()
576 ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL); in aspeed_sgpio_probe()
578 raw_spin_lock_init(&gpio->lock); in aspeed_sgpio_probe()
580 gpio->chip.parent = &pdev->dev; in aspeed_sgpio_probe()
581 gpio->chip.ngpio = nr_gpios * 2; in aspeed_sgpio_probe()
582 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask; in aspeed_sgpio_probe()
583 gpio->chip.direction_input = aspeed_sgpio_dir_in; in aspeed_sgpio_probe()
584 gpio->chip.direction_output = aspeed_sgpio_dir_out; in aspeed_sgpio_probe()
585 gpio->chip.get_direction = aspeed_sgpio_get_direction; in aspeed_sgpio_probe()
586 gpio->chip.request = NULL; in aspeed_sgpio_probe()
587 gpio->chip.free = NULL; in aspeed_sgpio_probe()
588 gpio->chip.get = aspeed_sgpio_get; in aspeed_sgpio_probe()
589 gpio->chip.set = aspeed_sgpio_set; in aspeed_sgpio_probe()
590 gpio->chip.set_config = aspeed_sgpio_set_config; in aspeed_sgpio_probe()
591 gpio->chip.label = dev_name(&pdev->dev); in aspeed_sgpio_probe()
592 gpio->chip.base = -1; in aspeed_sgpio_probe()
594 aspeed_sgpio_setup_irqs(gpio, pdev); in aspeed_sgpio_probe()
596 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_sgpio_probe()
611 MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");